{"title":"Analysis of Resistive Open Defects in a Synchronizer","authors":"Hyoung-Kook Kim, W. Jone, Laung-Terng Wang","doi":"10.1109/DFT.2009.34","DOIUrl":null,"url":null,"abstract":"This paper presents fault modeling and analysis for open defects in a synchronizer that is implemented by two D flip-flops. Open defects are injected into any node of the synchronizer, and HSPICE is used to perform circuit analysis. The major purpose of this analysis is to find all possible faults that might occur in the synchronizer by open defects. The results obtained can be used to develop methods for testing the interfacing circuits between different clock domains which are implemented with the synchronizer.","PeriodicalId":405651,"journal":{"name":"2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"150 45","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFT.2009.34","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
This paper presents fault modeling and analysis for open defects in a synchronizer that is implemented by two D flip-flops. Open defects are injected into any node of the synchronizer, and HSPICE is used to perform circuit analysis. The major purpose of this analysis is to find all possible faults that might occur in the synchronizer by open defects. The results obtained can be used to develop methods for testing the interfacing circuits between different clock domains which are implemented with the synchronizer.
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