Towards effective and compression-friendly test of memory interface logic

Abstract

Cost and time-to-market considerations are strongly driving the need to improve the effectiveness of structural patterns for speed/voltage binning. In this paper we focus on improving the quality of testing memory interface paths for speed/voltage-binning. We propose DFT schemes that propagate faults through the memory that are effective with test compression. We also propose memory architectural enhancements to improve the effectiveness of ATPG patterns for Fmax identification. Both synchronous and asynchronous memories are targeted. Experimental results on an industrial ASIC core show the effectiveness of the proposed schemes with test compression. Initial silicon results from a 40-nm testchip is also presented and it proves that Fmax using the proposed scheme is very close to that of functional patterns, while Fmax using conventional schemes are more than 2X higher than that of functional patterns.