Hardware-Efficient FPGA-Based Approximate Multipliers for Error-Tolerant Computing

Abstract

With the increasing demand for data processing, approximate computing is widely used in various fault-tolerant applications such as image processing, computer vision and machine learning. These applications also require a huge number of multiplication operations. In this paper, we are mainly oriented to the softcore approximate multiplier which is implemented on FPGA via encoding the INIT parameter values in the Look-Up-Table (LUT) primitives. Three approximate multipliers with associated carry chain are presented in the manner of reducing LUTs from proposed exact multiplier. An approximate multiplier without carry chain is also presented to further reduce the multiplier's critical path delay and power consumption. We also present an accuracy configurable adder to build high-order approximate multipliers for architectural space exploration. The resolution of the state-of-the-art Mean Relative Error Distance (MRED) and Power-Delay Product (PDP) pareto front is improved and the approximate multiplier we proposed achieves 24.4%, 52.9% and 56.4% reduction in latency, area, and power over the soft multiplier IP core, respectively. Finally, we apply the proposed approximate multiplier design to image processing and convolutional neural networks (CNNs). Compared to advanced approximate multipliers, it offers less energy consumption and area while remaining acceptable qualities. Our designs are open sourced at https://github.com/Yaoshangshang96/FPGA-based_approx_mult to assist further reproducing and development.