ASIC Implementation of 4 Bit Multipliers

Abstract

Recently, several experimental systems based on programmable logic have been designed and implemented which are programmed using a hardware design methodology. One necessary component of the software environment will be a library of standard macrocells corresponding to commonly used arithmetic and logical operations. In this paper Array multiplier is designed specially for programmable logic. This multiplier is cellular, highly pipelined and uses only of local interconnections. In the later part of this paper exposure to Booth multiplier and Wallace tree multiplier also has been given which is one of the reduction techniques for multipliers. The design is particularly carried out for a 4-bit multiplier.