3D-DPS: An Efficient 3D-CAC for Reliable Data Transfer in 3D ICs

Abstract

Migration to Three Dimensional Integrated Circuits (3D ICs) can provide higher scalability, higher throughput, and lower power consumption with respect to Two Dimensional Integrated Circuits (2D ICs). Also, the latency bottleneck of interconnections in 2D ICs is efficiently solved in 3D ICs. This is due to the use of Through-Silicon-Vias (TSVs) in the communication structure of 3D ICs. TSVs are among the efficient fabrication mechanisms that connect stacked layers in 3D ICs. However, proximity and large size of TSVs make them highly prone to crosstalk faults. Crosstalk faults can cause mutual undesired influences between TSVs and thus seriously threat the reliability of data transfer on TSVs. The severity of TSV-to-TSV crosstalk faults depend on the transition patterns appearing on the TSVs. To reduce the crosstalk faults in TSVs, this paper intends to propose Fibonacci-based 3D-Crosstalk Avoidance Code (3D-CAC) called 3D-Doubled Penultimate Summation-based (3D-DPS) CAC. 3D-DPS can completely omit 3D-Tripple opposite Direction Transition (3D-TOD) and is applicable to any arbitrary width of 3×N TSV mesh. 3D-DPS has not ambiguity in representing code words and generates unique code word for each data word. In addition, 3D-DPS considers overlaps between transitions of 3×N TSV meshs by using a mechanism called Coding Window. Evaluation results show that 3D-DPS reduces the area occupation, power consumption and critical path of codec by 53.0%, 25.2% and 1.5%, respectively in comparison with state-of-the-art 3D-CAC.