An Improved Miller Compensated Two Stage CMOS Operational Amplifier

Abstract

The design of a power efficient and high speed integrated circuits is complex and even more challenging with the current trend towards reduced supply voltages. The work presented in this paper is a High gain, High slew rate, wide band two-stage compensated CMOS operational amplifier. An uncompensated operational amplifier is prone various instability problems. Modified Miller compensation scheme with Cascoded current mirrors and pole zero cancelation techniques are utilized in this design to overcome the various instability problems mentioned in this work. The proposed work involves assumptions of specifications for a specific application, theoretical design calculations, simulation and verification using Cadence tools. In order to verify the theoretical designed values, the proposed compensated two stage CMOS operational amplifier was designed and simulated in 90nm CMOS technology using Cadence Virtuoso tool at an operating voltage of VDD=1.8V. The important parameters such as direct current gain, phase margin, power dissipation, CMRR, unity gain-bandwidth, slew rate was verified with the theoretical values.