Novel stable sram for ultra low power deep submicron cache memories

Abstract

Power consumption and stability happen to be of great concern in the deep-submicron SRAM cell design. In this paper, the design and functionality of a novel ultra low power stable SRAM cell is discussed which addresses power minimization as well as stability against large variation in temperature which is ideally suited for space applications. This paper explores a novel circuit level approach to reduce power in the SRAM cell during active mode of operation as well as standby mode by incorporating NMOS-PMOS pair in each pull down path. During active mode power reduction takes place by increasing the impedance of the ground path and thus reducing the current. In the idle mode, the state of the SRAM cell is retained to a good logic-1(0) value and sub threshold leakage is reduced by utilizing stack effect. It is found that this cell operating at a supply voltage value of 0.5V, using 50nm BSIM models resulted in about 19X power savings in active mode and 21X times in stand-by state-retention mode. Better stability is also reported with large variations in temperature when compared to the standard 6-T SRAM cell and other representative low leakage power SRAM cells due to self controlling feedback. The NMOS- PMOS pair provides the compensation against the linear dependence of current on temperature. This novel cell achieves excellent active mode power minimization (which is usually not addressed in SRAM designs which achieve standby mode power minimization) along with good leakage power reduction.