Countermeasure techniques for SEED hardware modules against differential power analysis

Abstract

SEED, the Korean standard block cipher algorithm, is a 128-bit symmetric key block cipher algorithm. Although SEED is theoretically safe, cryptographic devices with SEED modules are vulnerable to differential power analysis due to leakage information. Recently, differential power analysis has been widely researched, and various countermeasure techniques against differential power analysis have been proposed. In this paper, we embodied SEED hardware modules with differential power analysis countermeasure techniques using masking methods, and we generated random number using simple PRNG module. We embodied the SEED hardware modules using VHDL, and analyzed the result of simulation and synthesis.