Complementary LDMOS transistors for a CMOS/BiCMOS process

Abstract

This paper describes a methodology of using multiple implants that are self-aligned to the poly gate edge to form an LDMOS. This allows the implementation of complementary LDMOS devices onto existing CMOS/BiCMOS processes without the addition of any thermal treatments thereby having no effect on the existing CMOS/BiCMOS device performance. This approach gives greater flexibility in controlling the body doping profile in the lateral and vertical directions enabling threshold voltage (Vt) and breakdown voltage (BV) optimization for a wide range of source junctions that exist in many intrinsic and foundry processes.