An experimental 4Mb CMOS DRAM

Abstract

technology developments were performed, in addition to the use of previously-established technologies, some of which have been demonstrated for 1 M CMOS DRAMs”~. The RAM was fabricated in a twintub CMOS process with 1 . 0 ~ design rules, which are affordable minimum limits for VLSIs obtained by present aligners. The array consists of trenched, N-channel, depletion-type capacitor cells in a P-well, which helps to reduce soft error rate314. Figure 1 shows a cross-sectional SEM microphotograph of the cell. Cell storage capacitance is 40fF with a 31-1 deep trench. Even though they are not necessari1y needed for Vcc/2 for precharged bitlines, dummy cells having a full memory cell capacitance and Vcc /2 level are adopted making the sense amplifiers less susceptible to bitline precharge level variations. Memory cell, dummy cell, and sense amplifier circuitry are shown in Figure 2. Considering a transition from llrl to 4M, many problems become more serious. One of these problems is operating current. The RAM is divided into eight 512K blocks. Together with Vcc/2 bitline precharge, one fourth of the blocks is activated during each RAS operating cycle to reduce power dissipation due to bitline discharge. However, the active current and especially the peak current are still not small enough to neglect since these are causes of V c c and VSS noise. Thus, an exclusive power supply wiring technique for sense amplifiers is applied to avoid the effect of bitline discharge and reduce current noise in peripheral circuit operation. Since memory test time markedly increases with memory size, the RAM has an 8b parallel test mode operation which suppresses the RAM test time. This mode is available for both x1 and x4 packaged device testing as well as for die sort testing. The test mode is activated by applying a high voltage to an extra TEN (test enable) pad. To obtain a high quality 4M DRAM, several new circuit and process