A novel SOI trench LDMOS with vertical double-RESRUF layer

Abstract

A novel SOI trench LDMOS with vertical double-RESURF is studied in this paper. A p-type silicon pillar is inserted beside the oxide trench as a vertical double RESURF layer, which can effectively modulate the electronic field and enhance the doping concentration in the drift region. The drain n+ region extends to the surface of buried oxide layer, shortening the motion-path in the high-resistance n− drift region for the carriers. A significantly optimized dependence of specific on-resistance on breakdown voltage is obtained.