Pub Date : 2017-12-01DOI: 10.1109/EDSSC.2017.8126507
G. Liou, Chun‐Hu Cheng, Y. Chiu
In this work, we investigated the photocapacitive effect of the metal-ferroelectric-insulator-semiconductor capacitors under illumination. The photocapacitive effect is mainly caused by light photon excitation, contributed from the variation of depletion charge. We suggested that the ferroelectric domains are affected by defect dipole charges formed by the interface trapped charges to lead to the variation of depletion capacitance.
{"title":"Photocapacitive effect of ferroelectric hafnium-zirconate capacitor structure","authors":"G. Liou, Chun‐Hu Cheng, Y. Chiu","doi":"10.1109/EDSSC.2017.8126507","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126507","url":null,"abstract":"In this work, we investigated the photocapacitive effect of the metal-ferroelectric-insulator-semiconductor capacitors under illumination. The photocapacitive effect is mainly caused by light photon excitation, contributed from the variation of depletion charge. We suggested that the ferroelectric domains are affected by defect dipole charges formed by the interface trapped charges to lead to the variation of depletion capacitance.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126942645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EDSSC.2017.8333243
J. Liou, Y. Chang, Kuan-Wen Fang
Raman spectrum of a graphene edge, showing the main raman features, the D band(˜1350 cm-1), G band(˜1580 cm-1) and 2D band (˜2700 cm-1) taken with a laser excitation energy of 2.41 eV. D band is not easy to be found in the good structure of the graphite, generally D band and G band integral intensity ratio ID / IG, to determine whether the carbon material defects and the crystallization of the pros and cons, but D band is usually also the incident light wavelength with the impact of the incident area. The insert voltage conditions with H2SO4 and KOH is demo in the study. The D band and G band integral intensity ratio ID/ IG is equal 1.08, and FWHM(cm-1) is equal 97.6 value.
{"title":"Investigated raman spectroscopy of graphene material properties","authors":"J. Liou, Y. Chang, Kuan-Wen Fang","doi":"10.1109/EDSSC.2017.8333243","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8333243","url":null,"abstract":"Raman spectrum of a graphene edge, showing the main raman features, the D band(˜1350 cm<sup>-1</sup>), G band(˜1580 cm<sup>-1</sup>) and 2D band (˜2700 cm<sup>-1</sup>) taken with a laser excitation energy of 2.41 eV. D band is not easy to be found in the good structure of the graphite, generally D band and G band integral intensity ratio I<sup>D</sup> / I<sup>G</sup>, to determine whether the carbon material defects and the crystallization of the pros and cons, but D band is usually also the incident light wavelength with the impact of the incident area. The insert voltage conditions with H<sub>2</sub>SO<sub>4</sub> and KOH is demo in the study. The D band and G band integral intensity ratio I<sup>D</sup>/ I<sup>G</sup> is equal 1.08, and FWHM(cm<sup>-1</sup>) is equal 97.6 value.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133325062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EDSSC.2017.8355965
Y. Ma, L. Liu, W. Tang, P. Lai
Pentacene organic thin-film transistors (OTFTs) with high-k NdON gate dielectric incorporating different Ti contents are fabricated and their physical and electrical characteristics are studied. With appropriate Ti content, the OTFT with NdTiON as gate dielectric can achieve improved performance, e.g. a carrier mobility of 0.80 cm2/V·s, a small threshold voltage of -1.25 V, and a small sub-threshold swing of 0.13 V/dec. The AFM results of the pentacene layer and the dielectric layer reveal that incorporating Ti into NdON can obtain a smoother dielectric surface, which should be due to the suppressed hygroscopicity of Nd oxide caused by the Ti incorporation. Both the smoother dielectric surface and thus larger pentacene grains grown are responsible for the improved carrier mobility of the device.
{"title":"Improved performance of pentacene OTFT by incorporating Ti in NdON gate dielectric","authors":"Y. Ma, L. Liu, W. Tang, P. Lai","doi":"10.1109/EDSSC.2017.8355965","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8355965","url":null,"abstract":"Pentacene organic thin-film transistors (OTFTs) with high-k NdON gate dielectric incorporating different Ti contents are fabricated and their physical and electrical characteristics are studied. With appropriate Ti content, the OTFT with NdTiON as gate dielectric can achieve improved performance, e.g. a carrier mobility of 0.80 cm2/V·s, a small threshold voltage of -1.25 V, and a small sub-threshold swing of 0.13 V/dec. The AFM results of the pentacene layer and the dielectric layer reveal that incorporating Ti into NdON can obtain a smoother dielectric surface, which should be due to the suppressed hygroscopicity of Nd oxide caused by the Ti incorporation. Both the smoother dielectric surface and thus larger pentacene grains grown are responsible for the improved carrier mobility of the device.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131175770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EDSSC.2017.8126403
Hiroya Sato, M. Yanagisawa, T. Yoshimasu
This paper presents a highly linear 28-GHz band SOI CMOS power amplifier with an adaptive bias circuit for cascode MOSFET for next generation wireless communication. The power amplifier consists of a cascode MOSFET, the adaptive bias circuit and the input and output matching circuits. The power amplifier has exhibited a simulated output P1dB (1-dB gain compression point) of 19.2 dBm and a PAE of 39.0 %.
{"title":"A 28-GHz band highly linear power amplifier with novel adaptive bias circuit for cascode MOSFET in 56-nm SOI CMOS","authors":"Hiroya Sato, M. Yanagisawa, T. Yoshimasu","doi":"10.1109/EDSSC.2017.8126403","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126403","url":null,"abstract":"This paper presents a highly linear 28-GHz band SOI CMOS power amplifier with an adaptive bias circuit for cascode MOSFET for next generation wireless communication. The power amplifier consists of a cascode MOSFET, the adaptive bias circuit and the input and output matching circuits. The power amplifier has exhibited a simulated output P1dB (1-dB gain compression point) of 19.2 dBm and a PAE of 39.0 %.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129027860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EDSSC.2017.8126469
Hong-Wun Gao, Yeong-Her Wang, Y. Ko, T. Chiang
Based on the parabolic potential approach (PPA) and equivalent number of gates (ENG), a new quasi-3-D subthreshold current/swing model for the fully depleted quadruple-Gate (FDQG) MOSFET is developed. The model explicitly shows how the channel length, gate oxide thickness, and silicon film thickness affect the subthreshold current/swing behavior. The model is verified by its calculated results matching well with those of the three-dimensional device simulator and can be used to investigate the subthreshold current/swing for the short-channel QG MOSFETs.
{"title":"A new quasi-3-D subthreshold current/swing model for fully-depleted quadruple-gate (FDQG) MOSFETs","authors":"Hong-Wun Gao, Yeong-Her Wang, Y. Ko, T. Chiang","doi":"10.1109/EDSSC.2017.8126469","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126469","url":null,"abstract":"Based on the parabolic potential approach (PPA) and equivalent number of gates (ENG), a new quasi-3-D subthreshold current/swing model for the fully depleted quadruple-Gate (FDQG) MOSFET is developed. The model explicitly shows how the channel length, gate oxide thickness, and silicon film thickness affect the subthreshold current/swing behavior. The model is verified by its calculated results matching well with those of the three-dimensional device simulator and can be used to investigate the subthreshold current/swing for the short-channel QG MOSFETs.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127818976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8333264
S. Lai, Wing-Shan Tam, C. Kok, H. Wong
In this paper, the linearity of the magnetic sensitivity of split-drain magnetic field effect transistor (SSD-MAGFET) is studied, where experimental results have shown that the magnetic sensitivity over wide magnetic field strength shows a piecewise linear response with respect to applied magnetic field strength. Furthermore, the experimental results also showed that the piecewise linear response depends on the sector angle of the SSD-MAGFET. Previous studies have attributed these properties to the channel boundary trapping effect. The underlying charge trapping behavior are investigated by three-dimensional numerical device simulation. The simulation results match well with experimental measurements, which is strong evidence that the the physics of piecewise linear magnetic sensitivity of SSD-MAGFET is attributed to the channel boundary charge trapping.
{"title":"A study on split-drain MAGFET channel boundary charge trapping based on numerical simulation","authors":"S. Lai, Wing-Shan Tam, C. Kok, H. Wong","doi":"10.1109/EDSSC.2017.8333264","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8333264","url":null,"abstract":"In this paper, the linearity of the magnetic sensitivity of split-drain magnetic field effect transistor (SSD-MAGFET) is studied, where experimental results have shown that the magnetic sensitivity over wide magnetic field strength shows a piecewise linear response with respect to applied magnetic field strength. Furthermore, the experimental results also showed that the piecewise linear response depends on the sector angle of the SSD-MAGFET. Previous studies have attributed these properties to the channel boundary trapping effect. The underlying charge trapping behavior are investigated by three-dimensional numerical device simulation. The simulation results match well with experimental measurements, which is strong evidence that the the physics of piecewise linear magnetic sensitivity of SSD-MAGFET is attributed to the channel boundary charge trapping.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"316 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123142986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126440
Jinnan Ding, Shuguo Li
Large number addition is the fundamental operation in cryptography algorithms. In this paper, we accelerate large addition in hardware design by introducing non-least-positive form, which is beneficial to parallel processing. An implementation of 256-bit signed array accumulator with our method shows an improvement of 18% in speed and 15% in area-delay product compared with traditional design.
{"title":"A trick for parallel accumulation of signed array","authors":"Jinnan Ding, Shuguo Li","doi":"10.1109/EDSSC.2017.8126440","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126440","url":null,"abstract":"Large number addition is the fundamental operation in cryptography algorithms. In this paper, we accelerate large addition in hardware design by introducing non-least-positive form, which is beneficial to parallel processing. An implementation of 256-bit signed array accumulator with our method shows an improvement of 18% in speed and 15% in area-delay product compared with traditional design.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"7 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115735724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126406
T. Wang, Y. Wan
Study of electron transport in nanopillar transistor at 300K shows that elastic vibration is an intrinsic behavior of the device. The frequency observed in the drain-source current is found to agree with the charging frequency. Given a quantum dot of size 10×10×9nm3, the maximum displacement is estimated to be 0.3nm. Once the displacement diminishes to zero, single-electron tunnel becomes the dominating effect. A forced vibration model is proposed to explain the correlation between surface charges and vibrations. When the distribution of charges is uniformly on each SiNx atom, vibration becomes stable and can yield homogenous damping current.
{"title":"Evidence of coulomb blockade induced alternating current in nanopillar transistor","authors":"T. Wang, Y. Wan","doi":"10.1109/EDSSC.2017.8126406","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126406","url":null,"abstract":"Study of electron transport in nanopillar transistor at 300K shows that elastic vibration is an intrinsic behavior of the device. The frequency observed in the drain-source current is found to agree with the charging frequency. Given a quantum dot of size 10×10×9nm3, the maximum displacement is estimated to be 0.3nm. Once the displacement diminishes to zero, single-electron tunnel becomes the dominating effect. A forced vibration model is proposed to explain the correlation between surface charges and vibrations. When the distribution of charges is uniformly on each SiNx atom, vibration becomes stable and can yield homogenous damping current.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125570413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126476
Hung-Wei Chen, Shao-Chang Huang, Mi-Chang Chang, Jen-Hang Yang, Tingyou Lin
Since large array devices of MOSFETs are huge for driving capabilities, ESD self protections are also required. Then, the large drain-contact-to-poly-gate-spacing layout rule is usually adopted with large layout areas. In this paper, a new control circuit is implemented for adopting the minimum device layout rule in the LAD. Hence, it results in a very small layout area and ESD self-protection capabilities can be established.
{"title":"ESD protection and driving capability switch control circuits for large array NMOSFET driving devices","authors":"Hung-Wei Chen, Shao-Chang Huang, Mi-Chang Chang, Jen-Hang Yang, Tingyou Lin","doi":"10.1109/EDSSC.2017.8126476","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126476","url":null,"abstract":"Since large array devices of MOSFETs are huge for driving capabilities, ESD self protections are also required. Then, the large drain-contact-to-poly-gate-spacing layout rule is usually adopted with large layout areas. In this paper, a new control circuit is implemented for adopting the minimum device layout rule in the LAD. Hence, it results in a very small layout area and ESD self-protection capabilities can be established.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126947045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-01DOI: 10.1109/EDSSC.2017.8126434
Xiaoxin Guo, M. Cai, Xiaoyong He
An op-ampless second-order compensated bandgap reference with low temperature coefficient is proposed in this paper. The bandgap is second-order curvature-compensated by the temperature coefficient of the threshold voltage of a MOSFET. Simulated by Spectre, the output reference voltage is 1.102V with a 2.7ppm temperature coefficient from −40 °C to 160 °C and a −60dB PSRR at low frequency. The current dissipation of the whole circuit is 16μA. The layout area is 0.029mm2.
{"title":"A low power op-ampless bandgap reference with second-order compensation","authors":"Xiaoxin Guo, M. Cai, Xiaoyong He","doi":"10.1109/EDSSC.2017.8126434","DOIUrl":"https://doi.org/10.1109/EDSSC.2017.8126434","url":null,"abstract":"An op-ampless second-order compensated bandgap reference with low temperature coefficient is proposed in this paper. The bandgap is second-order curvature-compensated by the temperature coefficient of the threshold voltage of a MOSFET. Simulated by Spectre, the output reference voltage is 1.102V with a 2.7ppm temperature coefficient from −40 °C to 160 °C and a −60dB PSRR at low frequency. The current dissipation of the whole circuit is 16μA. The layout area is 0.029mm2.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114895884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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