Model parameter generation for high-performance circuit simulation

Abstract

The geometry dependence of standard MOS model parameters requires that specific model parameter sets have to be known for each transistor size. In view of the large number of sizes currently used in circuit design, the common use of polynomial fits and tables was deemed to be too restrictive in the designer's choice of transistor size or too inaccurate for circuit simulation. This is particularly true for analog design. Therefore, a new procedure has been developed and introduced into the design strategy. This permits unlimited choice of device geometry without reducing the precision of the circuit simulation. The proposed solution allows the continued use of standard SPICE MOS models and even increases simulation accuracy and reliability by calculating model parameter sets for all individual transistor sizes. It also standardizes the transition from measurement and model parameter extraction to electrical-circuit analysis. The need to simulate statistical behavior is implemented in a user-friendly way.<>