Four phase clocking rule for energy efficient digital circuits — An adiabatic concept

Abstract

The energy consumption issue is efficiently addressed by adiabatic switching technique in design of low power digital circuits. Adiabatic switching technique offers the reducing in energy dissipation during switching events and recycling the load capacitance energy instead of dissipated as heat. But adiabatic circuits highly depend upon power clock and parameter variations. With the help of clocking rule, the digital circuits such as inverter and inverter chain are designed for adiabatic techniques, 2N-2N2P, Efficient Charge Recovery Logic (ECRL), Positive Feedback Adiabatic Logic (PFAL) and Clocked Adiabatic Logic (CAL) using TSPICE simulation. The results show high energy savings as compared to CMOS circuits in specified frequency range.