VLSI architecture and implementation of statistical multiplexer

Abstract

In networking data rate varies from application to application and usually ratio of peak data rate is much higher than average data rate i.e. bursty data transfer. Hence, service provider/Network cannot use normal multiplexing as it requires huge bandwidth with very small utilization factor, so there is a requirement of statistical multiplexer, which is based on incoming data rate statistics and efficiently utilizes the available total bandwidth. There are many applications which use this technique like asynchronous transfer mode, UDP/TCP protocol, and digital TV transmission, digital broadcasting. Generally hardware implementation is faster than software implementation, so authors have proposed VLSI hardware architecture of statistical multiplexer and implemented on FPGA using Xilinx ISE. Various modules are simulated, synthesized and implemented on FPGA. Digital operating clock frequency is also estimated for individual sub-module and integrated main module.