Scalable hybrid verification of complex microprocessors

M. Mneimneh, F. Aloul, Christopher T. Weaver, Saugata Chatterjee, K. Sakallah, T. Austin
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引用次数: 24

Abstract

We introduce a new verification methodology for modern microprocessors that uses a simple checker processor to validate the execution of a companion high-performance processor. The checker can be viewed as an at-speed emulator that is formally verified to be compliant to an ISA specification. This verification approach enables the practical deployment of formal methods without impacting overall performance.
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复杂微处理器的可扩展混合验证
我们为现代微处理器引入了一种新的验证方法,该方法使用简单的检查处理器来验证伴随的高性能处理器的执行。检查器可以看作是经过正式验证符合ISA规范的高速仿真器。这种验证方法支持正式方法的实际部署,而不会影响总体性能。
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False coupling interactions in static timing analysis Scalable hybrid verification of complex microprocessors System-level power/performance analysis for embedded systems design Automated pipeline design Test strategies for BIST at the algorithmic and register-transfer levels
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