W. Qiu, Wenkai Wu, S. Luo, P. Kornetzky, I. Batarseh
{"title":"Practical design considerations of a single-stage single-switch parallel PFC converter for universal voltage applications","authors":"W. Qiu, Wenkai Wu, S. Luo, P. Kornetzky, I. Batarseh","doi":"10.1109/IAS.2002.1043826","DOIUrl":null,"url":null,"abstract":"In this paper, a single-stage single-switch power factor correction (PFC) converter with parallel power flow function is presented. By adding a secondary winding to the boost inductor, this topology will directly transfer some input power to the load, resulting in two flow paths for the load power. While still achieving high power factor, it will reduce the current stresses on power components and limit the maximum voltage across intermediate bus capacitors. Operational principle and practical design considerations are discussed in details. A 150 W prototype based on this topology has been built and tested in the lab with experimental results that show good performance.","PeriodicalId":202482,"journal":{"name":"Conference Record of the 2002 IEEE Industry Applications Conference. 37th IAS Annual Meeting (Cat. No.02CH37344)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Conference Record of the 2002 IEEE Industry Applications Conference. 37th IAS Annual Meeting (Cat. No.02CH37344)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IAS.2002.1043826","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
In this paper, a single-stage single-switch power factor correction (PFC) converter with parallel power flow function is presented. By adding a secondary winding to the boost inductor, this topology will directly transfer some input power to the load, resulting in two flow paths for the load power. While still achieving high power factor, it will reduce the current stresses on power components and limit the maximum voltage across intermediate bus capacitors. Operational principle and practical design considerations are discussed in details. A 150 W prototype based on this topology has been built and tested in the lab with experimental results that show good performance.