{"title":"A Volterra series approach for the design of low-voltage CG-CS active baluns","authors":"Shan He, C. Saavedra","doi":"10.1109/ICUWB.2012.6340391","DOIUrl":null,"url":null,"abstract":"A low-voltage active balun and amplifier is presented. The circuit uses a common-gate common-source (CG-CS) noise-cancelling topology with a simple distortion cancellation method to improve the IIP3 performance of the balun-amplifier. A Volterra series analysis is employed to provide insights into the nonlinear behavior of the circuit. A chip was fabricated and the experimental test results show an average voltage gain for the balun-amplifier of 16.2 dB and a maximum IIP3 of -3.8 dBm over the span of 0.3-2.4 GHz. The circuit exhibits a noise figure below 4.0 dB over the measured band and reaches a minimum of 3.2 dB. The chip uses a single 0.9 V dc supply and consumes 15.8 mW of power. The RFIC was fabricated using a standard 130 nm CMOS process.","PeriodicalId":260071,"journal":{"name":"2012 IEEE International Conference on Ultra-Wideband","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE International Conference on Ultra-Wideband","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICUWB.2012.6340391","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
A low-voltage active balun and amplifier is presented. The circuit uses a common-gate common-source (CG-CS) noise-cancelling topology with a simple distortion cancellation method to improve the IIP3 performance of the balun-amplifier. A Volterra series analysis is employed to provide insights into the nonlinear behavior of the circuit. A chip was fabricated and the experimental test results show an average voltage gain for the balun-amplifier of 16.2 dB and a maximum IIP3 of -3.8 dBm over the span of 0.3-2.4 GHz. The circuit exhibits a noise figure below 4.0 dB over the measured band and reaches a minimum of 3.2 dB. The chip uses a single 0.9 V dc supply and consumes 15.8 mW of power. The RFIC was fabricated using a standard 130 nm CMOS process.