Modeling of STI-induced stress phenomena in CMOS 90nm Flash technology

Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850) Pub Date : 2004-11-15 DOI:10.1109/ESSDER.2004.1356574

P. Fantini, G. Giuga, S. Schippers, A. Marmiroli, G. Ferrari

引用次数: 5

Abstract

A non negligible layout sensitivity of MOSFETS electrical behavior has been recently observed in advanced CMOS technologies. Some efforts have been attempted to encapsulate this phenomenon in Spice-like simulation oriented models. In the present work, we suggest improvements to previously proposed approaches, after a critical discussion about them. An extensive characterization of CMOS 90 nm Flash memory technology is the support of our issues. Finally, simulation of prototype circuits shed some light on the impact of STI stress in IC design.

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CMOS 90nm Flash技术中sti诱导应力现象的建模

近年来，在先进的CMOS技术中已经观察到mosfet电学行为的不可忽略的布局灵敏度。一些人试图将这种现象封装在Spice-like模拟面向模型中。在目前的工作中，我们建议改进先前提出的方法，经过对它们的批判性讨论。广泛表征的CMOS 90纳米闪存技术是我们的问题的支持。最后，对原型电路进行了仿真，揭示了STI应力对集成电路设计的影响。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)

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