Optimization of the self-aligned GaAs MESFET with the multilayer dielectric “dummy gate“ for a high power microwave applications

Abstract

The results of the influence of GaAs MESFET geometry on the transistor parameters have been presented. The self-aligned ion implantation process with the multilayer SiO2 “dummy gate” for the transistors fabrication was used. The dependences of the breakdown voltage and drain-source current of the fabricated GaAs MESFET versus the gap between the gate and n+ drain region were plotted. The optimal design of the transistor to achieve the required high-power performance has been found.