A simulation framework for 3-dimension Networks-on-chip with different vertical channel density configurations

Abstract

3D ICs are emerging as a promising solution for scalability, power and performance demands of next generation Systems-on-Chip (SoCs). Along with the advantages, it also imposes a number of challenges with respect to cost, technological reliability, thermal budget and so forth. Networks-on-chip (NoCs), which is thoroughly investigated in 2D SoCs design as scalable interconnects, is also well relevant to 3D IC Design. The cost of moving from 2D to 3D should be justified with improvements in performance, power or latency. To solve this problem, this paper presents a new simulation framework for 3D NoCs. We established a new Generic Scalable Pseudo Application (GSPA), where user can generate their own scalable pseudo applications. We have also integrated the state-of-the-art benchmarks to evaluate the 3D NoC system. In the framework, the 3D NoC with different vertical channel densities (VD) (i.e. number of Through-Silicon-Vias (TSVs)) can be generated according to the preference of users. After the simulation, the power consumption and system performance are evaluated. We have compared 2D NoC architecture with 3D NoC architecture with different VDs. The experimental results show that 3D architectures have significant advantage (Avg. 51%, 44%, 35% for 100%, 50%, 25% VD, respectively) in the aspect of interconnect power delay product in comparison to 2D mesh architecture. The 25% VD architecture is the best choice with 17% advantage over full connection (100% VD) 3D NoC architecture in the aspect of Figure of Merit which takes area and TSV connection yield into account among all the experiments for the given constrains.