Wafer Level Packaging by residual stress evaluation using piezoresistive stress sensors for the enhancement of reliability

Abstract

Wafer Level Packaging (WLP) is the technology which it is an IC package completely fabricated at the wafer level and assembled with standard SMT. WLP technology is one of promising technology which make it possible a low-cost and a high reliability packaging. Significant reductions in device form factor and cost have been achieved, while at the same time increasing the electrical performance. In this article, it is shown that the process and design for WLP were enhanced by the measurement of residual stress quantatively using the stress sensor of the piezoresistive type. The piezoresistive stress sensors can be used as a useful and sutible tool for stress measurement on chips inside wafer level packaging. It has also already been demonstrated that piezoresistive sensors are in-site, real-time, nondestructive, efficient, and cost-effective in the measurement of stress inside microelectronic packaging.