Pub Date : 2010-07-12DOI: 10.1109/iemt.2008.5507852
Jenson Lee, J. Sjoberg, D. Rooney, D. Geiger, D. Shangguan
Conductive adhesives have been widely used in die mounting and component terminal bonding in certain types of hybrid circuits for a number of years. ECA (Electrically conductive adhesive) is an alternative to lead-free solder for certain specific applications in electronic products. Low processing temperature, fine pitch, flexible process steps, and no flux residues are some of the major advantages when using ECA for electrical interconnection between SMDs (surface mount devices) and the printed circuit board (PCB) in SMT (surface mount technology). ECA use a polymer matrix (such as epoxy) filled with conducting fillers (such as copper or silver); silver is used commonly due to its high conductivity and wide availability. The particle size (typically less than 40 microns) is controlled by the screen mesh used to sort the fillers. The study results indicated that it is feasible to incorporate ICA into current SMT production lines and can provide an alternative for solder replacement for specific product applications.
{"title":"Process development and reliability evaluation of Electrically conductive adhesives (ECA) for low temperature SMT assembly","authors":"Jenson Lee, J. Sjoberg, D. Rooney, D. Geiger, D. Shangguan","doi":"10.1109/iemt.2008.5507852","DOIUrl":"https://doi.org/10.1109/iemt.2008.5507852","url":null,"abstract":"Conductive adhesives have been widely used in die mounting and component terminal bonding in certain types of hybrid circuits for a number of years. ECA (Electrically conductive adhesive) is an alternative to lead-free solder for certain specific applications in electronic products. Low processing temperature, fine pitch, flexible process steps, and no flux residues are some of the major advantages when using ECA for electrical interconnection between SMDs (surface mount devices) and the printed circuit board (PCB) in SMT (surface mount technology). ECA use a polymer matrix (such as epoxy) filled with conducting fillers (such as copper or silver); silver is used commonly due to its high conductivity and wide availability. The particle size (typically less than 40 microns) is controlled by the screen mesh used to sort the fillers. The study results indicated that it is feasible to incorporate ICA into current SMT production lines and can provide an alternative for solder replacement for specific product applications.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134226563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-01DOI: 10.1109/IEMT.2008.5507837
W. T. Ling, E. P. Leng, N. Amin, I. Ahmad
In the recent years, lead-free solder material have been increasingly applied to the green semiconductor products for RoHS compliance. For Flip Chip Plastic Ball Grid Array (FCPBGA), recent industry trend is changing from ENIG pad finishing to Solder-on-pad (SOP) pad finishing using Sn3.0Ag0.5Cu to improve board level reliability due to black pad issue on ENIG pads. However, SOP has posted a challenge in ball attachment process due to higher oxide level on SOP pads. The use of Sn3.8AgO. 7Cu solder ball on SOP pad finishing has been facing slanted ball and wrinkled ball issues after ball attach reflow. Slanted ball is a defect as it fails the solder ball radius-trueposition and coplanarity specification. In this paper, Sn3.5Ag solder ball on 33 × 33 FCPBGA with SOP was being compared to conventional Sn3.8AgO.7Cu solder ball. After assembly, samples were subjected to laser scanning for slanted ball inspection. Visual inspection under low power scope was done to check for wrinkled balls. Cold ball pull (CBP) was used to evaluate the solder joint strength at 3 conditions, namely after assembly (TO), after six time reflow and after 168 hours high temperature storage (HTS). In addition, tray drop test and packing drop test were conducted to assess solder joint integrity due to handling and impact force. Solderability test was also performed per Jedec standard to assess board mounting reliability. Finally, Sn3.5Ag is recommended to replace Sn3.8AgO.7Cu ball for 33 × 33mm FCPBGA package to resolve the wrinkled and slanted ball issue and improve the overall solder joint reliability.
{"title":"Lead-free solder ball attach improvement on FCPBGA with SOP pad finishing","authors":"W. T. Ling, E. P. Leng, N. Amin, I. Ahmad","doi":"10.1109/IEMT.2008.5507837","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507837","url":null,"abstract":"In the recent years, lead-free solder material have been increasingly applied to the green semiconductor products for RoHS compliance. For Flip Chip Plastic Ball Grid Array (FCPBGA), recent industry trend is changing from ENIG pad finishing to Solder-on-pad (SOP) pad finishing using Sn3.0Ag0.5Cu to improve board level reliability due to black pad issue on ENIG pads. However, SOP has posted a challenge in ball attachment process due to higher oxide level on SOP pads. The use of Sn3.8AgO. 7Cu solder ball on SOP pad finishing has been facing slanted ball and wrinkled ball issues after ball attach reflow. Slanted ball is a defect as it fails the solder ball radius-trueposition and coplanarity specification. In this paper, Sn3.5Ag solder ball on 33 × 33 FCPBGA with SOP was being compared to conventional Sn3.8AgO.7Cu solder ball. After assembly, samples were subjected to laser scanning for slanted ball inspection. Visual inspection under low power scope was done to check for wrinkled balls. Cold ball pull (CBP) was used to evaluate the solder joint strength at 3 conditions, namely after assembly (TO), after six time reflow and after 168 hours high temperature storage (HTS). In addition, tray drop test and packing drop test were conducted to assess solder joint integrity due to handling and impact force. Solderability test was also performed per Jedec standard to assess board mounting reliability. Finally, Sn3.5Ag is recommended to replace Sn3.8AgO.7Cu ball for 33 × 33mm FCPBGA package to resolve the wrinkled and slanted ball issue and improve the overall solder joint reliability.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122279641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-01DOI: 10.1109/IEMT.2008.5507840
E. P. Leng, Min Ding, W. T. Ling, N. Amin, I. Ahmad, M. Lee, A. Haseeb
A study was conducted on BGA lead-free C5 solder joint system to compare SnAgNiCo versus conventional Sn3.8Ag0.7Cu solder alloy. This study showed that SnAgNiCo C5 solder system performed better than Sn3.8Ag0.7Cu in terms of joint strength and brittle mode failure. Shear and pull strength was measured by Dage which is representative of the intermetallic (IMC) strength between the C5 solder sphere and Cu/Ni/Au pad finishing. Tray drop test and packing drop test were done to gauge solder joint performance against handling and impact force. A comprehensive study was done to study the effect of microstructure and interface intermetallics of both solder system after assembly, after test, after high temperature storage (HTS) at 150°C for 168 hours and 504 hours and after 6x reflow towards the joint integrity. Microstructure studies on SnAgNiCo solder reveals that formation of rod shape Ag3Sn IMC distributed across the solder surface helps to act as dispersion hardening that increases the mechanical strength for the SnAgNiCo solder after thermal aging. EDX analysis confirmed that in SnAgCu solder/Ni interface, Cu-rich IMC formed on top of the Ni-rich IMC. For SnAgNiCo system, only Ni-rich IMC is found. Therefore, it is highly suspected that the presence of Cu-rich IMC posed a detrimental effect on the joint strength and tends to cause brittle joint failure. Both of the effect is then showed in ball pull result that after 6x reflow, SnAgCu solder has 100% brittle mode failure, where SnAgNiCo solder has only 5%. This result correlates with missing ball responses after packing drop tests. Thus, SnAgNiCo lead-free solder is a potential candidate for lead-free solder joint improvement for overall lead-free package robustness.
{"title":"A comparison study on SnAgNiCo and Sn3.8Ag0.7Cu C5 lead free solder system","authors":"E. P. Leng, Min Ding, W. T. Ling, N. Amin, I. Ahmad, M. Lee, A. Haseeb","doi":"10.1109/IEMT.2008.5507840","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507840","url":null,"abstract":"A study was conducted on BGA lead-free C5 solder joint system to compare SnAgNiCo versus conventional Sn3.8Ag0.7Cu solder alloy. This study showed that SnAgNiCo C5 solder system performed better than Sn3.8Ag0.7Cu in terms of joint strength and brittle mode failure. Shear and pull strength was measured by Dage which is representative of the intermetallic (IMC) strength between the C5 solder sphere and Cu/Ni/Au pad finishing. Tray drop test and packing drop test were done to gauge solder joint performance against handling and impact force. A comprehensive study was done to study the effect of microstructure and interface intermetallics of both solder system after assembly, after test, after high temperature storage (HTS) at 150°C for 168 hours and 504 hours and after 6x reflow towards the joint integrity. Microstructure studies on SnAgNiCo solder reveals that formation of rod shape Ag3Sn IMC distributed across the solder surface helps to act as dispersion hardening that increases the mechanical strength for the SnAgNiCo solder after thermal aging. EDX analysis confirmed that in SnAgCu solder/Ni interface, Cu-rich IMC formed on top of the Ni-rich IMC. For SnAgNiCo system, only Ni-rich IMC is found. Therefore, it is highly suspected that the presence of Cu-rich IMC posed a detrimental effect on the joint strength and tends to cause brittle joint failure. Both of the effect is then showed in ball pull result that after 6x reflow, SnAgCu solder has 100% brittle mode failure, where SnAgNiCo solder has only 5%. This result correlates with missing ball responses after packing drop tests. Thus, SnAgNiCo lead-free solder is a potential candidate for lead-free solder joint improvement for overall lead-free package robustness.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125048316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-01DOI: 10.1109/IEMT.2008.5507777
M. Alias, P. Leisher, K. Choquette, S. Shaari
In this paper, fan-pad metallization and trench patterning were introduced in 850 nm Vertical-Cavity Surface-Emitting Laser (VCSEL) device packaging. Low threshold current and series resistance, which contributes to higher VCSEL efficiency, are obtained for the VCSEL with fan-metallization and trench patterning fabricated devices. Further, the output spectral characteristics show stable multimode operation for these devices. The results indicate that the proposed VCSEL packaging exhibits superior device performance compared to typical packaged VCSEL with square-pad metal.
{"title":"High efficiency 850 nm Vertical-Cavity Surface-Emitting Laser using fan-pad metallization and trench patterning","authors":"M. Alias, P. Leisher, K. Choquette, S. Shaari","doi":"10.1109/IEMT.2008.5507777","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507777","url":null,"abstract":"In this paper, fan-pad metallization and trench patterning were introduced in 850 nm Vertical-Cavity Surface-Emitting Laser (VCSEL) device packaging. Low threshold current and series resistance, which contributes to higher VCSEL efficiency, are obtained for the VCSEL with fan-metallization and trench patterning fabricated devices. Further, the output spectral characteristics show stable multimode operation for these devices. The results indicate that the proposed VCSEL packaging exhibits superior device performance compared to typical packaged VCSEL with square-pad metal.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123125732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507876
D. Manessis, R. Aschenbrenner, A. Ostmann, H. Reichl
Stencil printing of solder paste remains the technology route of choice for flip chip bumping because of its economical advantages over traditionally costly evaporation and electroplating processes. Fraunhofer IZM printing group has developed stencil printing processes to meet the current trends in wafer bumping roadmaps with continuous increase of I/O's and reduced bumping pitch. Mainstream wafer bumping has been performed by using innovative Type 5 (15-25μm) and Type 6 (5-15μm) pastes with both Sn-Pb and Pb-free compositions from 300 μm up to 100 μm pitches for peripheral pad configurations and up to 120 μm for area array configurations. At R&D level, IZM has advanced stencil printing very close to its technological limits at pitches even down to 50 μm. Innovative electroformed and laser-cut with nano-treatment stencils have been manufactured with an extreme thinness of 20 μm for bumping wafers at Ultra fine pitches (UFP) of 100 μm, 80 μm and 60 μm. Specifically, for 100 μm pitch bumping, both type 7 (2-11μm) and type 6 (5-15μm) pastes of eutectic composition Sn63/Pb37 have been successfully employed. Bumping using 25 μm electroformed stencil thickness has yielded bump heights of 42.3±3.8μm and 43.6±3.5μm for type 7 and type 6 pastes, respectively. A newly prototype developed type 8 paste (2-8μm) has been used for the first time to bump chips with peripheral contacts at 80 μm and 60 μm pitch. Bumping at 80 μm pitch with nano-treated laser-cut stencil has yielded bumps of 28 μm in height. For bumping at 60 μm pitch, a 20 μm thick electroformed stencil was used with 35 μmx80 μm oblong apertures. Printing at 60 μm pitch has yielded very promising results and has proved the capability of electroformed technology to manufacture accurate and robust thin stencils. The bump height at 60 μm pitch was measured to be 28 ±3 μm. Paste-in-Resist technology lias been developed as an alternative to stencils in order to overcome the manufacturing difficulties of making extremely small apertures. Paste is printed in resist apertures which have been opened by photolithographic processes. In this way, bumping has been demonstrated up to 50 μm pitches. Complimentary to stencil printing processes, IZM has developed balling technologies up to 400 μm pitch up to 8" wafers with a thickness of 150 μm. Solder balling can be achieved either by "perform ball print" using conventional stencil printers with specially designed stencils or by "ball drop" techniques. Balling technologies have demonstrated the application of 300 μm and 250 μm Sn-Pb and Pb-free balls at respective area array pitches of 500 μm and 400 μm, the main I/O pitches for WL-CSP bumping.
{"title":"Latest developments in bumping technologies for flip chip and WLCSP packaging","authors":"D. Manessis, R. Aschenbrenner, A. Ostmann, H. Reichl","doi":"10.1109/IEMT.2008.5507876","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507876","url":null,"abstract":"Stencil printing of solder paste remains the technology route of choice for flip chip bumping because of its economical advantages over traditionally costly evaporation and electroplating processes. Fraunhofer IZM printing group has developed stencil printing processes to meet the current trends in wafer bumping roadmaps with continuous increase of I/O's and reduced bumping pitch. Mainstream wafer bumping has been performed by using innovative Type 5 (15-25μm) and Type 6 (5-15μm) pastes with both Sn-Pb and Pb-free compositions from 300 μm up to 100 μm pitches for peripheral pad configurations and up to 120 μm for area array configurations. At R&D level, IZM has advanced stencil printing very close to its technological limits at pitches even down to 50 μm. Innovative electroformed and laser-cut with nano-treatment stencils have been manufactured with an extreme thinness of 20 μm for bumping wafers at Ultra fine pitches (UFP) of 100 μm, 80 μm and 60 μm. Specifically, for 100 μm pitch bumping, both type 7 (2-11μm) and type 6 (5-15μm) pastes of eutectic composition Sn63/Pb37 have been successfully employed. Bumping using 25 μm electroformed stencil thickness has yielded bump heights of 42.3±3.8μm and 43.6±3.5μm for type 7 and type 6 pastes, respectively. A newly prototype developed type 8 paste (2-8μm) has been used for the first time to bump chips with peripheral contacts at 80 μm and 60 μm pitch. Bumping at 80 μm pitch with nano-treated laser-cut stencil has yielded bumps of 28 μm in height. For bumping at 60 μm pitch, a 20 μm thick electroformed stencil was used with 35 μmx80 μm oblong apertures. Printing at 60 μm pitch has yielded very promising results and has proved the capability of electroformed technology to manufacture accurate and robust thin stencils. The bump height at 60 μm pitch was measured to be 28 ±3 μm. Paste-in-Resist technology lias been developed as an alternative to stencils in order to overcome the manufacturing difficulties of making extremely small apertures. Paste is printed in resist apertures which have been opened by photolithographic processes. In this way, bumping has been demonstrated up to 50 μm pitches. Complimentary to stencil printing processes, IZM has developed balling technologies up to 400 μm pitch up to 8\" wafers with a thickness of 150 μm. Solder balling can be achieved either by \"perform ball print\" using conventional stencil printers with specially designed stencils or by \"ball drop\" techniques. Balling technologies have demonstrated the application of 300 μm and 250 μm Sn-Pb and Pb-free balls at respective area array pitches of 500 μm and 400 μm, the main I/O pitches for WL-CSP bumping.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125096127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507880
B. Poobalan, K. Cheong, Ung Boon Hoe, Resch Roland
This paper discusses a new concept for the self-aligned contact implantation for Infineon power transistors. Instead of utilizing side wall spacers, which are formed by Tetraethylorthosilicate (TEOS) deposition followed by an anisotropic TEOS etch, the contact implantation is facilitated after the contact hole-etch process. By applying this concept, a number of process steps can be removed, which as a consequence greatly reduces the frontend production cost of a wafer. Additionally, defect density baseline as well as cycle time of the wafer is significantly reduced. Several design of experiments were performed in order to achieve the same electrical performance as compared to the original concept. Special consideration has been given on the analysis of the transistor parameters, such as `on resistance', `threshold voltage' and `transconductance'. The results are presented and discussed clearly showing the potential of the new concept.
{"title":"A new concept of self-aligned contact implantation for power devices","authors":"B. Poobalan, K. Cheong, Ung Boon Hoe, Resch Roland","doi":"10.1109/IEMT.2008.5507880","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507880","url":null,"abstract":"This paper discusses a new concept for the self-aligned contact implantation for Infineon power transistors. Instead of utilizing side wall spacers, which are formed by Tetraethylorthosilicate (TEOS) deposition followed by an anisotropic TEOS etch, the contact implantation is facilitated after the contact hole-etch process. By applying this concept, a number of process steps can be removed, which as a consequence greatly reduces the frontend production cost of a wafer. Additionally, defect density baseline as well as cycle time of the wafer is significantly reduced. Several design of experiments were performed in order to achieve the same electrical performance as compared to the original concept. Special consideration has been given on the analysis of the transistor parameters, such as `on resistance', `threshold voltage' and `transconductance'. The results are presented and discussed clearly showing the potential of the new concept.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124573795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507784
Seung Seoup Lee, Jong Whan Baik, J. S. Kim, H. Jeon, Sung Yi
Wafer Level Packaging (WLP) is the technology which it is an IC package completely fabricated at the wafer level and assembled with standard SMT. WLP technology is one of promising technology which make it possible a low-cost and a high reliability packaging. Significant reductions in device form factor and cost have been achieved, while at the same time increasing the electrical performance. In this article, it is shown that the process and design for WLP were enhanced by the measurement of residual stress quantatively using the stress sensor of the piezoresistive type. The piezoresistive stress sensors can be used as a useful and sutible tool for stress measurement on chips inside wafer level packaging. It has also already been demonstrated that piezoresistive sensors are in-site, real-time, nondestructive, efficient, and cost-effective in the measurement of stress inside microelectronic packaging.
{"title":"Wafer Level Packaging by residual stress evaluation using piezoresistive stress sensors for the enhancement of reliability","authors":"Seung Seoup Lee, Jong Whan Baik, J. S. Kim, H. Jeon, Sung Yi","doi":"10.1109/IEMT.2008.5507784","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507784","url":null,"abstract":"Wafer Level Packaging (WLP) is the technology which it is an IC package completely fabricated at the wafer level and assembled with standard SMT. WLP technology is one of promising technology which make it possible a low-cost and a high reliability packaging. Significant reductions in device form factor and cost have been achieved, while at the same time increasing the electrical performance. In this article, it is shown that the process and design for WLP were enhanced by the measurement of residual stress quantatively using the stress sensor of the piezoresistive type. The piezoresistive stress sensors can be used as a useful and sutible tool for stress measurement on chips inside wafer level packaging. It has also already been demonstrated that piezoresistive sensors are in-site, real-time, nondestructive, efficient, and cost-effective in the measurement of stress inside microelectronic packaging.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114328053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507844
Bih Wen Fon, H. Tan, Kok Kee Yang
In the fast-paced semiconductor industry, the need for innovative package solutions arises in order to cope with emerging miniaturization trend. Micro leadless land grid array (μLLGA) surpasses other plastic encapsulated packages with remarkable profile of 0.38mm. As one of the thinnest packages available in the market up to date, the unique structure of μLLGA is illustrated in this paper. As we know, there are many limitations in thin die advancement from the point of wafer manufacturing, machine capability and assembly challenges. In view of that, copper etching process has come to play an essential role in μLLGA assembly. This report discusses the mandatory Copper etching process using alkaline etchant that contributes to the thin package profile. Prior to the characterization of machine parameters, it is crucial to understand the chemical equilibrium of echant chemical. A full factorial DOE was conducted to characterize the factors that affect Copper etching efficiency. The four main factors included in this study are Bath Temperature, Conveyor Speed, Nozzle Pressure and Bath Specific Gravity. The etching efficiency is determined by many observations after etching process. Compound discoloration is being observed to ensure no cosmetic defect due to chemical spraying. This report also addresses the package robustness through SAT observation. Special lead frame design contributes to the passing of reliability test at MSL 1. Solderability test for this fine pitch package is also being studied in this paper, comparing the typical dip-and-look and surface mount solderability test method. From the experiment, key parameters that affect etching efficiency have been identified to be Bath Temperature and Conveyor Speed. With optimized parameters and good chemical maintenance, an effective copper etching process can be realized.
{"title":"Characterization of copper etching process on micro leadless land grid array (ゼLLGA) via design of experiments approach","authors":"Bih Wen Fon, H. Tan, Kok Kee Yang","doi":"10.1109/IEMT.2008.5507844","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507844","url":null,"abstract":"In the fast-paced semiconductor industry, the need for innovative package solutions arises in order to cope with emerging miniaturization trend. Micro leadless land grid array (μLLGA) surpasses other plastic encapsulated packages with remarkable profile of 0.38mm. As one of the thinnest packages available in the market up to date, the unique structure of μLLGA is illustrated in this paper. As we know, there are many limitations in thin die advancement from the point of wafer manufacturing, machine capability and assembly challenges. In view of that, copper etching process has come to play an essential role in μLLGA assembly. This report discusses the mandatory Copper etching process using alkaline etchant that contributes to the thin package profile. Prior to the characterization of machine parameters, it is crucial to understand the chemical equilibrium of echant chemical. A full factorial DOE was conducted to characterize the factors that affect Copper etching efficiency. The four main factors included in this study are Bath Temperature, Conveyor Speed, Nozzle Pressure and Bath Specific Gravity. The etching efficiency is determined by many observations after etching process. Compound discoloration is being observed to ensure no cosmetic defect due to chemical spraying. This report also addresses the package robustness through SAT observation. Special lead frame design contributes to the passing of reliability test at MSL 1. Solderability test for this fine pitch package is also being studied in this paper, comparing the typical dip-and-look and surface mount solderability test method. From the experiment, key parameters that affect etching efficiency have been identified to be Bath Temperature and Conveyor Speed. With optimized parameters and good chemical maintenance, an effective copper etching process can be realized.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126484443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507888
M. H. Othman, Z. Ahmad, H. Akil
Polyimide is a choice of material widely used in electronic packaging due to its high thermal and mechanical stability and low thermal expansion coefficient and dielectric constant. Two porous polyimides of structure shown in the following figure were successfully synthesised. The reaction scheme involve polycondensation of 3,3',4,4'-biphenyltetracarboxylic dianhydride with 4",4'''-(hexafluoroisopropyllidene)-bis(4-phenoxyaniline) and 4,4'-(4,4'-isopropylidenediphenyl-1,1'-diyldioxy) dianiline followed by thermal curing of the intermediate polyamic acid. This treatment afforded a high molecular mass polyimide of tough and thermally stable polymer. Nanofoam polyimide films were fabricated by means of sol-gel technique to give a homogeneously dispersed nano-sized voids in range 100-400 nm. Both materials showed an ultra-low dielectric constant of 2.76 and 2.84 respectively. Comparison of the treated and non-treated polyimide films showed that the gain in low dielectric constant is achieved at a considerable expanse of mechanical properties.
{"title":"Fabrication of nanoporous polyimide of low dielectric constant","authors":"M. H. Othman, Z. Ahmad, H. Akil","doi":"10.1109/IEMT.2008.5507888","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507888","url":null,"abstract":"Polyimide is a choice of material widely used in electronic packaging due to its high thermal and mechanical stability and low thermal expansion coefficient and dielectric constant. Two porous polyimides of structure shown in the following figure were successfully synthesised. The reaction scheme involve polycondensation of 3,3',4,4'-biphenyltetracarboxylic dianhydride with 4\",4'''-(hexafluoroisopropyllidene)-bis(4-phenoxyaniline) and 4,4'-(4,4'-isopropylidenediphenyl-1,1'-diyldioxy) dianiline followed by thermal curing of the intermediate polyamic acid. This treatment afforded a high molecular mass polyimide of tough and thermally stable polymer. Nanofoam polyimide films were fabricated by means of sol-gel technique to give a homogeneously dispersed nano-sized voids in range 100-400 nm. Both materials showed an ultra-low dielectric constant of 2.76 and 2.84 respectively. Comparison of the treated and non-treated polyimide films showed that the gain in low dielectric constant is achieved at a considerable expanse of mechanical properties.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133504386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/IEMT.2008.5507846
Yeoh Tay Jin, Yeoh Teong San, Song Chia Li
Semiconductor manufacturing faces numerous challenges and increased complexity in yield improvement, defect reduction and equipment related issues. Innovation is a key element to stay ahead of the competitors. Typically the way towards idea generation is Brainstorming. While it is easy to use, it is very much dependent on the experience and knowledge of the group of people. For new engineers, there is a certain degree of compromise to the solutions. This paper will introduce a systematic innovation methodology called Theory of Inventive Problem Solving (TRIZ). It is a structured methodology for modeling the problem, tools to work with the models and finally models of solutions. TRIZ is a recognized international science of creativity, based on the laws of physics and innovative patents distilled to numerous problem solving tools. It is a toolbox with 12 tools which provide the engineers with methods to create breakthrough ideas. This paper will describe 5 TRIZ methods (Trimming, Contradiction, 40 Inventive Principles, Process Analysis, Trends of Engineering System Evolution) and case studies will be shared.
{"title":"TRIZ: Systematic innovation towards factory operational efficiency","authors":"Yeoh Tay Jin, Yeoh Teong San, Song Chia Li","doi":"10.1109/IEMT.2008.5507846","DOIUrl":"https://doi.org/10.1109/IEMT.2008.5507846","url":null,"abstract":"Semiconductor manufacturing faces numerous challenges and increased complexity in yield improvement, defect reduction and equipment related issues. Innovation is a key element to stay ahead of the competitors. Typically the way towards idea generation is Brainstorming. While it is easy to use, it is very much dependent on the experience and knowledge of the group of people. For new engineers, there is a certain degree of compromise to the solutions. This paper will introduce a systematic innovation methodology called Theory of Inventive Problem Solving (TRIZ). It is a structured methodology for modeling the problem, tools to work with the models and finally models of solutions. TRIZ is a recognized international science of creativity, based on the laws of physics and innovative patents distilled to numerous problem solving tools. It is a toolbox with 12 tools which provide the engineers with methods to create breakthrough ideas. This paper will describe 5 TRIZ methods (Trimming, Contradiction, 40 Inventive Principles, Process Analysis, Trends of Engineering System Evolution) and case studies will be shared.","PeriodicalId":151085,"journal":{"name":"2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"34 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133448409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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