Low Latency Recovery from Transient Faults for Pipelined Processor Architectures

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools Pub Date : 2010-09-01 DOI:10.1109/DSD.2010.87

M. Jeitler, J. Lechner

引用次数: 4

Abstract

Recent technology trends have made radiation-induced soft errors a growing threat to the reliability of microprocessors, a problem previously only known to the aerospace industry. Therefore, the ability to handle higher soft error rates in modern processor architectures is essential in order to allow further technology scaling. This paper presents an efficient fault-tolerance method for pipeline-based processors using temporal redundancy. Instructions are executed twice at each pipeline stage, which allows the detection of transient faults. Once a fault is detected the execution is stopped immediately and recovery is implicitly performed within the pipeline stages. Due to this fast reaction the fault is contained at its origin and no expensive rollback operation is required later on.

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流水线处理器体系结构瞬态故障的低延迟恢复

最近的技术趋势使得辐射引起的软错误对微处理器的可靠性构成越来越大的威胁，这个问题以前只有航空航天工业才知道。因此，为了允许进一步的技术扩展，在现代处理器架构中处理更高的软错误率的能力是必不可少的。本文提出了一种利用时间冗余对基于流水线的处理器进行容错的方法。指令在每个管道阶段执行两次，这允许检测瞬态故障。一旦检测到故障，执行将立即停止，并在管道阶段内隐式执行恢复。由于这种快速反应，故障被控制在原点，以后不需要昂贵的回滚操作。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools

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