A CMOS adiabatic inverter operating with a single clock power supply to reduce non-adiabatic loss

Abstract

This paper presents the design of a low energy CMOS adiabatic inverter (Ib-driver). The proposed Ib-driver structure uses complementary input, output and a dual-rail structure. When implemented on a 0.13 mum CMOS 1.2 V technology, under the large capacitive loading condition, Ib-driver performs better than the reference adiabatic circuit (sk-driver) in terms of the energy-delay product (21%), with active area which is (34%) lower. Proposed inverter has a full swing for high capacitive loads (20 pF).