Pub Date : 2008-12-03DOI: 10.1109/APCCAS.2008.4746247
Chien-Hung Kuo, Kuan-Yi Lee, Shuo Chen
In this paper, a 0.8 V switched-opamp (SOP)-based 2-2 cascade delta-sigma modulator for wideband applications is presented. The first stage uses low-distortion topology to release the requirement of SOP due to only the quantization noise in integrator path. The second stage employs a CIFB structure without the use of summer in front of the quantizer to decrease the power consumption. Double sampling technique combined with the SOP with two output stages is used to promote the clock efficiency. The proposed fourth-order DeltaSigma modulator with CIFFCIFB structure has been implemented in a 0.13 mum CMOS 1P8M technology. The core area excluding PADs is 1.66times1.62 mm2. The peak signal-to-noise plus distortion ratio (SNDR) and dynamic range (DR) of the presented modulator within a 1.1 MHz of bandwidth are 77.9 dB and 85 dB, respectively, under a 20 MHz of clock rate. The power dissipation of the presented DeltaSigma modulator is 15.7 mW at a 0.8 V of supply voltage.
{"title":"A 0.8V SOP-based cascade multibit delta-sigma modulator for wideband applications","authors":"Chien-Hung Kuo, Kuan-Yi Lee, Shuo Chen","doi":"10.1109/APCCAS.2008.4746247","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746247","url":null,"abstract":"In this paper, a 0.8 V switched-opamp (SOP)-based 2-2 cascade delta-sigma modulator for wideband applications is presented. The first stage uses low-distortion topology to release the requirement of SOP due to only the quantization noise in integrator path. The second stage employs a CIFB structure without the use of summer in front of the quantizer to decrease the power consumption. Double sampling technique combined with the SOP with two output stages is used to promote the clock efficiency. The proposed fourth-order DeltaSigma modulator with CIFFCIFB structure has been implemented in a 0.13 mum CMOS 1P8M technology. The core area excluding PADs is 1.66times1.62 mm2. The peak signal-to-noise plus distortion ratio (SNDR) and dynamic range (DR) of the presented modulator within a 1.1 MHz of bandwidth are 77.9 dB and 85 dB, respectively, under a 20 MHz of clock rate. The power dissipation of the presented DeltaSigma modulator is 15.7 mW at a 0.8 V of supply voltage.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130122330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-03DOI: 10.1109/APCCAS.2008.4746267
A. Acharyya, K. Maharatna, B. Al-Hashimi
This paper surveys ongoing research for pervasive healthcare system development, highlights the associated technical challenges and outlines some possible future topics that require innovative research. We present a conceptual high level system overview for pervasive healthcare including a resource constrained architecture for extracting fetal electrocardiogram from maternal composite abdominal signal as a case study.
{"title":"Hardware development for pervasive healthcare systems: Current status and future directions","authors":"A. Acharyya, K. Maharatna, B. Al-Hashimi","doi":"10.1109/APCCAS.2008.4746267","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746267","url":null,"abstract":"This paper surveys ongoing research for pervasive healthcare system development, highlights the associated technical challenges and outlines some possible future topics that require innovative research. We present a conceptual high level system overview for pervasive healthcare including a resource constrained architecture for extracting fetal electrocardiogram from maternal composite abdominal signal as a case study.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114666086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-01DOI: 10.1109/APCCAS.2008.4746393
C. Chang, Chi-Wu Huang, Kuo-Huang Chang, Yi-Cheng Chen, Chung-Cheng Hsieh
Advance Encryption Standard (AES) hardware implementation in FPGA as well as in ASIC has been intensely discussing, especially in high-throughput (over several tens Gbps). However, low area designs have also been investigated in recent years for the embedded hardware applications. This paper presents a 32-bit AES implementation with a low area of 156 slices and a throughput of 876 Mbps, which outperformed the best reported result of 648 Mbps throughput found in literature.
{"title":"High throughput 32-bit AES implementation in FPGA","authors":"C. Chang, Chi-Wu Huang, Kuo-Huang Chang, Yi-Cheng Chen, Chung-Cheng Hsieh","doi":"10.1109/APCCAS.2008.4746393","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746393","url":null,"abstract":"Advance Encryption Standard (AES) hardware implementation in FPGA as well as in ASIC has been intensely discussing, especially in high-throughput (over several tens Gbps). However, low area designs have also been investigated in recent years for the embedded hardware applications. This paper presents a 32-bit AES implementation with a low area of 156 slices and a throughput of 876 Mbps, which outperformed the best reported result of 648 Mbps throughput found in literature.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117036218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-01DOI: 10.1109/APCCAS.2008.4746386
Youhua Shi, N. Togawa, M. Yanagisawa, T. Ohtsuki
This paper presents a new unknown response masking technique to minimize the effect on test loss due to overmasking. Unlike previous works where the scan responses are masked before entering the response compactor, the proposed method could mask the Xs when they are transformed on the scan path. Meanwhile, the masking cells are inserted along the scan paths, thus they would have no degradation on the performance of the designs. In addition, the test data required to mask unknown responses is only one bit for each test pattern. Experimental results show the effectiveness of the proposed method.
{"title":"Unknown response masking with minimized observable response loss and mask data","authors":"Youhua Shi, N. Togawa, M. Yanagisawa, T. Ohtsuki","doi":"10.1109/APCCAS.2008.4746386","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746386","url":null,"abstract":"This paper presents a new unknown response masking technique to minimize the effect on test loss due to overmasking. Unlike previous works where the scan responses are masked before entering the response compactor, the proposed method could mask the Xs when they are transformed on the scan path. Meanwhile, the masking cells are inserted along the scan paths, thus they would have no degradation on the performance of the designs. In addition, the test data required to mask unknown responses is only one bit for each test pattern. Experimental results show the effectiveness of the proposed method.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131083420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-01DOI: 10.1109/APCCAS.2008.4745973
Yu-Cheng Su, Shuenn-Yuh Lee, Angus Lin
An automatic gain control (AGC) circuit composed of a variable gain amplifier (VGA), a peak detector (PD), and a non-linear controller (NC) for digital hearing aid is proposed. To achieve low power consumption under 0.6-V supply voltage with threshold voltage Vth of 0.5 V, the AGC has been operated in the sub-threshold region with body-driven input. Moreover, the gate-degeneration and bump-circuit techniques are adopted to improve the linearity. The chip has been fabricated in TSMC 0.18-mum standard CMOS process, 52 dB gain range can be achieved under the measured results. Besides, the power consumption of the whole circuit is lower than 1.8 muW under normal conditions and the peak signal to noise ratio (SNR) is 39 dB. The core area of the AGC is 0.933 mm times 0.828 mm.
{"title":"A 0.6-V 1.8-μW automatic gain control circuit for digital hearing aid","authors":"Yu-Cheng Su, Shuenn-Yuh Lee, Angus Lin","doi":"10.1109/APCCAS.2008.4745973","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4745973","url":null,"abstract":"An automatic gain control (AGC) circuit composed of a variable gain amplifier (VGA), a peak detector (PD), and a non-linear controller (NC) for digital hearing aid is proposed. To achieve low power consumption under 0.6-V supply voltage with threshold voltage Vth of 0.5 V, the AGC has been operated in the sub-threshold region with body-driven input. Moreover, the gate-degeneration and bump-circuit techniques are adopted to improve the linearity. The chip has been fabricated in TSMC 0.18-mum standard CMOS process, 52 dB gain range can be achieved under the measured results. Besides, the power consumption of the whole circuit is lower than 1.8 muW under normal conditions and the peak signal to noise ratio (SNR) is 39 dB. The core area of the AGC is 0.933 mm times 0.828 mm.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114676815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-01DOI: 10.1109/APCCAS.2008.4746120
Ryo Tamura, Masayuki Honma, N. Togawa, M. Yanagisawa, T. Ohtsuki, Makoto Satoh
Reconfigurable processors are those whose contexts are dynamically reconfigured while they are working. We focus on a reconfigurable processor called FE-GA (Flexible Engine/Generic ALU array) for digital media processing. Currently, FE-GA does not have its dedicated behavior synthesis tool. In this paper, we design FIR filters and propose an algorithm to map them onto it automatically. For given an order and coefficients of an FIR filter, the algorithm generates a dedicated assembly code which represents a given FIR filter for FE-GA. Then an editor called FEEditor reads the generated assembly code and implements its corresponding FIR filter on FE-GA. The proposed algorithm achieves automatic mapping of FIR filters of all orders within the range of the specification of FE-GA architecture. Furthermore, it is proved that a minimum cycle is achieved to execute FIR filtering if there is no thread switching.
{"title":"FIR filter design on Flexible Engine/Generic ALU array and its dedicated synthesis algorithm","authors":"Ryo Tamura, Masayuki Honma, N. Togawa, M. Yanagisawa, T. Ohtsuki, Makoto Satoh","doi":"10.1109/APCCAS.2008.4746120","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746120","url":null,"abstract":"Reconfigurable processors are those whose contexts are dynamically reconfigured while they are working. We focus on a reconfigurable processor called FE-GA (Flexible Engine/Generic ALU array) for digital media processing. Currently, FE-GA does not have its dedicated behavior synthesis tool. In this paper, we design FIR filters and propose an algorithm to map them onto it automatically. For given an order and coefficients of an FIR filter, the algorithm generates a dedicated assembly code which represents a given FIR filter for FE-GA. Then an editor called FEEditor reads the generated assembly code and implements its corresponding FIR filter on FE-GA. The proposed algorithm achieves automatic mapping of FIR filters of all orders within the range of the specification of FE-GA architecture. Furthermore, it is proved that a minimum cycle is achieved to execute FIR filtering if there is no thread switching.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131250458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746041
Junyan Yi, Gang Yang, Yuki Todo, Zheng Tang
Edge linking is a fundamental computer-vision task, viewed as a constrained optimization problem, it is NP hard- being isomorphic to the classical traveling salesman problem. In this paper, we propose an efficient Elastic Net method for edge linking of images. A dynamic parameter strategy is introduced into the Elastic Net, which enable the network to have superior search ability for edge points and converge sooner to optimal or near-optimal solutions. Simulations are conducted on a series of artificial images. The results confirm that this method effectively improves both the solution quality and convergence speed of the classical Elastic Net.
{"title":"An efficient Elastic Net method for edge linking of images","authors":"Junyan Yi, Gang Yang, Yuki Todo, Zheng Tang","doi":"10.1109/APCCAS.2008.4746041","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746041","url":null,"abstract":"Edge linking is a fundamental computer-vision task, viewed as a constrained optimization problem, it is NP hard- being isomorphic to the classical traveling salesman problem. In this paper, we propose an efficient Elastic Net method for edge linking of images. A dynamic parameter strategy is introduced into the Elastic Net, which enable the network to have superior search ability for edge points and converge sooner to optimal or near-optimal solutions. Simulations are conducted on a series of artificial images. The results confirm that this method effectively improves both the solution quality and convergence speed of the classical Elastic Net.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115495401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746315
C. Tanaphatsiri, W. Jaikla, M. Siripruchyanun
This article proposes a topology of current-mode improved Wheatstone bridge based on dual-output current differencing transconductance amplifier (DO-CDTA). The features of the proposed configuration are that: magnitude of output signal can be controlled via the input bias currents; the proposed circuit is low temperature sensitive, the circuit description is very simple. The circuit performances are depicted through PSPICE simulations, they show good agreement to theoretical anticipation and provide ability to measure small resistance changes at a wide range of frequency (more than 60 MHz). The power consumption is approximately 4.55 mW at ~1.5 V supply voltages.
{"title":"A current-mode wheatstone bridge employing only single DO-CDTA","authors":"C. Tanaphatsiri, W. Jaikla, M. Siripruchyanun","doi":"10.1109/APCCAS.2008.4746315","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746315","url":null,"abstract":"This article proposes a topology of current-mode improved Wheatstone bridge based on dual-output current differencing transconductance amplifier (DO-CDTA). The features of the proposed configuration are that: magnitude of output signal can be controlled via the input bias currents; the proposed circuit is low temperature sensitive, the circuit description is very simple. The circuit performances are depicted through PSPICE simulations, they show good agreement to theoretical anticipation and provide ability to measure small resistance changes at a wide range of frequency (more than 60 MHz). The power consumption is approximately 4.55 mW at ~1.5 V supply voltages.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123108098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746381
C. Helmstetter, V. Joloboff
The development of embedded systems requires the development of increasingly complex software and hardware platforms. Full system simulation makes it possible to run the exact binary embedded software including the operating system on a totally simulated hardware platform. Whereas most simulation environments do not support full system simulation, or do not use any hardware modeling techniques, or have combined different types of technology, SimSoC is developing a full system simulation architecture with an integrated approach relying only upon SystemC hardware modeling and transaction-level modeling abstractions (TLM) for communications. To simulate processors at reasonably high speed, SimSoC integrates instruction set simulators (ISS) as SystemC modules with TLM interfaces to the other platform components. The ISSpsilas use a variant approach of dynamic translation to run binary code. The dynamic translator uses pre-compiled code that consists of specialized functions for instruction execution, using partial evaluation techniques. It is generated by a configurable code generator, which makes it possible to tune the generated code to optimize simulation speed for the target software application.
{"title":"SimSoC: A SystemC TLM integrated ISS for full system simulation","authors":"C. Helmstetter, V. Joloboff","doi":"10.1109/APCCAS.2008.4746381","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746381","url":null,"abstract":"The development of embedded systems requires the development of increasingly complex software and hardware platforms. Full system simulation makes it possible to run the exact binary embedded software including the operating system on a totally simulated hardware platform. Whereas most simulation environments do not support full system simulation, or do not use any hardware modeling techniques, or have combined different types of technology, SimSoC is developing a full system simulation architecture with an integrated approach relying only upon SystemC hardware modeling and transaction-level modeling abstractions (TLM) for communications. To simulate processors at reasonably high speed, SimSoC integrates instruction set simulators (ISS) as SystemC modules with TLM interfaces to the other platform components. The ISSpsilas use a variant approach of dynamic translation to run binary code. The dynamic translator uses pre-compiled code that consists of specialized functions for instruction execution, using partial evaluation techniques. It is generated by a configurable code generator, which makes it possible to tune the generated code to optimize simulation speed for the target software application.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124392058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-01DOI: 10.1109/APCCAS.2008.4746272
Yuen-Haw Chang
A closed-loop switched-capacitor-based (SC) two-stage current-mode multiphase voltage doubler (MPVD) is proposed based on pulse-width-modulation (PWM) control to achieve low-power step-up DC-DC conversion. The SC-based converter needs no magnetic element, e.g. inductor and transformer, so I.C. fabrication will be promising for VLSI applications. This current-mode MPVD can obtain the high voltage gain just by using the least number of pumping capacitors, so it will save the fabrication areas more. Besides, by combining with a current source and PWM control, a closed-loop MPVD is realized not only to enhance regulation capability for different desired outputs, but also to reinforce output robustness against source noises. Here, some theoretical analysis includes state-space averaging model, steady-state/transient analysis, power efficiency, and system stability. Finally, the closed-loop current-mode MPVD is simulated by OrCAD, and the results are illustrated to show the efficacy of the proposed scheme.
{"title":"Two-stage current-mode multiphase voltage doubler based on PWM control","authors":"Yuen-Haw Chang","doi":"10.1109/APCCAS.2008.4746272","DOIUrl":"https://doi.org/10.1109/APCCAS.2008.4746272","url":null,"abstract":"A closed-loop switched-capacitor-based (SC) two-stage current-mode multiphase voltage doubler (MPVD) is proposed based on pulse-width-modulation (PWM) control to achieve low-power step-up DC-DC conversion. The SC-based converter needs no magnetic element, e.g. inductor and transformer, so I.C. fabrication will be promising for VLSI applications. This current-mode MPVD can obtain the high voltage gain just by using the least number of pumping capacitors, so it will save the fabrication areas more. Besides, by combining with a current source and PWM control, a closed-loop MPVD is realized not only to enhance regulation capability for different desired outputs, but also to reinforce output robustness against source noises. Here, some theoretical analysis includes state-space averaging model, steady-state/transient analysis, power efficiency, and system stability. Finally, the closed-loop current-mode MPVD is simulated by OrCAD, and the results are illustrated to show the efficacy of the proposed scheme.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124398389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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