Accelerating trace computation in post-silicon debug

Abstract

Post-silicon debug comprises a significant and highly variable fraction of the total development time for large chip designs. To accelerate post-silicon debug, BackSpace [1, 2] employs on-chip monitoring circuitry and off-chip formal analysis to provide a trace of states that lead up to a crash state. BackSpace employs repeated runs of the integrated circuit being debugged, which can be time consuming. This paper shows that correlation information characterizing the application running on the hardware up to the crash state can reduce the number of runs of the chip by up to 51%.