Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450510
Yu-Ming Yang, I. Jiang
Unlike the mature and highly automatic flow for digital layout generation, the existing method to generate an analog layout is far from automatic because it highly depends on the designer's expertise. Prior endeavors are mainly dedicated to analog placement because they consider only the device symmetry constraint. This paper raises the wiring symmetry issue to analog layout: wiring symmetry is as crucial as device symmetry. Hence, we propose an analog placement and global routing algorithm to consider both types of symmetry constraints. During placement, we utilize the device folding technique to enhance the flexibility and feasibility on symmetry. Our results show that our algorithm can produce a promising initial layout to speed up the analog design process.
{"title":"Analog placement and global routing considering wiring symmetry","authors":"Yu-Ming Yang, I. Jiang","doi":"10.1109/ISQED.2010.5450510","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450510","url":null,"abstract":"Unlike the mature and highly automatic flow for digital layout generation, the existing method to generate an analog layout is far from automatic because it highly depends on the designer's expertise. Prior endeavors are mainly dedicated to analog placement because they consider only the device symmetry constraint. This paper raises the wiring symmetry issue to analog layout: wiring symmetry is as crucial as device symmetry. Hence, we propose an analog placement and global routing algorithm to consider both types of symmetry constraints. During placement, we utilize the device folding technique to enhance the flexibility and feasibility on symmetry. Our results show that our algorithm can produce a promising initial layout to speed up the analog design process.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115445497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450411
Hidetoshi Matsuoka, Hiroshi Ikeda, H. Higuchi, Yoshinori Tomita
In this paper, we propose a new model construction method utilizing application specific physical information and present its application to SRAM yield calculation. The physical information is extracted as statistical distributions from past simulation results automatically. Experimental results show our method achieves 700x speed up over non modeling method and more than 10x speed up over the conventional modeling method. It requires only 5.3 samples to model a fifth order full cross term polynomial with 21 coefficients and is free from over-fitting and singular matrix problem. This modeling method can be a general approach to create models with application specific physical information.
{"title":"An accurate modeling method utilizing application-specific statistical information and its application to SRAM yield estimation","authors":"Hidetoshi Matsuoka, Hiroshi Ikeda, H. Higuchi, Yoshinori Tomita","doi":"10.1109/ISQED.2010.5450411","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450411","url":null,"abstract":"In this paper, we propose a new model construction method utilizing application specific physical information and present its application to SRAM yield calculation. The physical information is extracted as statistical distributions from past simulation results automatically. Experimental results show our method achieves 700x speed up over non modeling method and more than 10x speed up over the conventional modeling method. It requires only 5.3 samples to model a fifth order full cross term polynomial with 21 coefficients and is free from over-fitting and singular matrix problem. This modeling method can be a general approach to create models with application specific physical information.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"771 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127151206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450406
Jun Xu, Ge Zhang, Weiwu Hu
The m-out-of-n encoded asynchronous circuits are able to implement the truly delay-insensitive circuit operations, but they suffer from higher power dissipation due to the large amount of logic cells. Besides, the throughput of the circuits is also worse than the synchronous counterparts since the four-cycle handshake protocol requires inserting a “NULL” token between two adjacent valid data transmissions. In this paper, we first propose a power gating technique to reduce the leakage power consumption in the idle phase, then figure out a replication method to improve the throughput at the cost of area increase. The evaluation results show that about 85% of leakage power reduction can be obtained when the power gating scheme is employed, and 62% of throughput improvement can be acquired nearly without additional power penalty when both proposals are integrated.
{"title":"Optimizing power and throughput for m-out-of-n encoded asynchronous circuits","authors":"Jun Xu, Ge Zhang, Weiwu Hu","doi":"10.1109/ISQED.2010.5450406","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450406","url":null,"abstract":"The m-out-of-n encoded asynchronous circuits are able to implement the truly delay-insensitive circuit operations, but they suffer from higher power dissipation due to the large amount of logic cells. Besides, the throughput of the circuits is also worse than the synchronous counterparts since the four-cycle handshake protocol requires inserting a “NULL” token between two adjacent valid data transmissions. In this paper, we first propose a power gating technique to reduce the leakage power consumption in the idle phase, then figure out a replication method to improve the throughput at the cost of area increase. The evaluation results show that about 85% of leakage power reduction can be obtained when the power gating scheme is employed, and 62% of throughput improvement can be acquired nearly without additional power penalty when both proposals are integrated.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124970437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450405
A. More, B. Taskin
A simulation-based feasibility study of an intra-chip wireless interconnect system is presented. The wireless interconnect system is modelled in a 250 nm standard complementary metal-oxide semiconductor (CMOS) technology operating at typical conditions. A finite element method (FEM) based 3-D full-wave solver is used to perform the electromagnetic field analysis. In the field analysis, the effects of the radiation of an intra-chip wireless interconnect system operating at 16 GHz on the circuit devices and local metal interconnects at arbitrary distances from the antennas are investigated. It is shown that the transmission gain between the antennas is mostly unaffected by the presence of local metal interconnects. The transmission scattering parameter (s-parameter) between the radiating antenna and the metal interconnects is below −31.66 dB. The leakage current in the sub-threshold region of the transistors, caused by the antenna radiation induced voltages, is shown to be below 2.2 fA and decreasing with distance from the radiating antenna.
{"title":"Leakage current analysis for intra-chip wireless interconnects","authors":"A. More, B. Taskin","doi":"10.1109/ISQED.2010.5450405","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450405","url":null,"abstract":"A simulation-based feasibility study of an intra-chip wireless interconnect system is presented. The wireless interconnect system is modelled in a 250 nm standard complementary metal-oxide semiconductor (CMOS) technology operating at typical conditions. A finite element method (FEM) based 3-D full-wave solver is used to perform the electromagnetic field analysis. In the field analysis, the effects of the radiation of an intra-chip wireless interconnect system operating at 16 GHz on the circuit devices and local metal interconnects at arbitrary distances from the antennas are investigated. It is shown that the transmission gain between the antennas is mostly unaffected by the presence of local metal interconnects. The transmission scattering parameter (s-parameter) between the radiating antenna and the metal interconnects is below −31.66 dB. The leakage current in the sub-threshold region of the transistors, caused by the antenna radiation induced voltages, is shown to be below 2.2 fA and decreasing with distance from the radiating antenna.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124980186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450530
H. Homayoun, Shahin Golshan, E. Bozorgzadeh, A. Veidenbaum, F. Kurdahi
Leakage power has grown significantly and is a major challenge in SoC design. Among SoC's components, clock distribution network power accounts for a large portion of chip power. In this paper, we propose to deploy sleep transistor insertion (STI) in the clock tree in order to reduce leakage power. We characterize the effect of sleep transistor sharing and sizing on clock tree wakeup time, leakage power, and propagation delay. We use these characteristics during leakage power optimization. We present post synthesis sleep transistor insertion (PSSTI), a heuristic clustering algorithm for sleep transistor insertion with the objective of total power minimization in a given clock tree. Sleep transistor sharing and sizing are deployed in order to meet the clock skew and wakeup delay constraints. We explored the potential benefits of STI using a standard industrial VLSI-CAD flow including sleep-transistor insertion and routing after clock synthesis and place-and-route of the benchmark circuits. Our results show that clock tree leakage power is reduced by 19%–32% depending on the topology of the synthesized clock tree.
{"title":"Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks","authors":"H. Homayoun, Shahin Golshan, E. Bozorgzadeh, A. Veidenbaum, F. Kurdahi","doi":"10.1109/ISQED.2010.5450530","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450530","url":null,"abstract":"Leakage power has grown significantly and is a major challenge in SoC design. Among SoC's components, clock distribution network power accounts for a large portion of chip power. In this paper, we propose to deploy sleep transistor insertion (STI) in the clock tree in order to reduce leakage power. We characterize the effect of sleep transistor sharing and sizing on clock tree wakeup time, leakage power, and propagation delay. We use these characteristics during leakage power optimization. We present post synthesis sleep transistor insertion (PSSTI), a heuristic clustering algorithm for sleep transistor insertion with the objective of total power minimization in a given clock tree. Sleep transistor sharing and sizing are deployed in order to meet the clock skew and wakeup delay constraints. We explored the potential benefits of STI using a standard industrial VLSI-CAD flow including sleep-transistor insertion and routing after clock synthesis and place-and-route of the benchmark circuits. Our results show that clock tree leakage power is reduced by 19%–32% depending on the topology of the synthesized clock tree.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"310 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122728328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450493
Jianchao Lu, B. Taskin
A clock buffer polarity assignment method is proposed that considers the impact of capacitive load on the peak current. It is shown that the peak current on the supply rails of a buffer is a monotonically increasing function of its driving capacitance. Consequently, the polarity of a clock buffer is assigned based on its capacitive load. The proposed method can be applied to assign buffer polarity on any number of levels of the clock tree. In experiments, the peak current on the clock tree in each local area is reduced by 36.3% on average. The worse case peak current of all the local areas are reduced by 35.7% on average. The proposed method is implemented with a pseudo-polynomial dynamic programming scheme demonstrating runtimes under a minute.
{"title":"Clock buffer polarity assignment considering capacitive load","authors":"Jianchao Lu, B. Taskin","doi":"10.1109/ISQED.2010.5450493","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450493","url":null,"abstract":"A clock buffer polarity assignment method is proposed that considers the impact of capacitive load on the peak current. It is shown that the peak current on the supply rails of a buffer is a monotonically increasing function of its driving capacitance. Consequently, the polarity of a clock buffer is assigned based on its capacitive load. The proposed method can be applied to assign buffer polarity on any number of levels of the clock tree. In experiments, the peak current on the clock tree in each local area is reduced by 36.3% on average. The worse case peak current of all the local areas are reduced by 35.7% on average. The proposed method is implemented with a pseudo-polynomial dynamic programming scheme demonstrating runtimes under a minute.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128805626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450410
Takanori Date, Shiho Hagiwara, K. Masu, Takashi Sato
Monte Carlo simulations have been widely adopted for analyzing circuit properties, such as SRAM yield, under strong influence of process variations. Enormous calculation time is required in such a simulation due to the low defect probabilities. In this paper, we propose a robust shift-vector determination for mean-shift importance sampling, by which efficiency and stability of the Monte Carlo simulation is improved. In the proposed method, the hypersphere sampling is developed to autonomously find the optimal shift-vector. The sampling is also limited to the regions where meaningful contribution to the yield is recognized. Simulation examples reveal that the proposed technique stably and efficiently estimates yield of noise stabilities of an SRAM cell. At the failure probability of 10−10, the number of calculation trials has been reduced by six orders magnitude compared with a conventional Monte Carlo simulation.
{"title":"Robust importance sampling for efficient SRAM yield analysis","authors":"Takanori Date, Shiho Hagiwara, K. Masu, Takashi Sato","doi":"10.1109/ISQED.2010.5450410","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450410","url":null,"abstract":"Monte Carlo simulations have been widely adopted for analyzing circuit properties, such as SRAM yield, under strong influence of process variations. Enormous calculation time is required in such a simulation due to the low defect probabilities. In this paper, we propose a robust shift-vector determination for mean-shift importance sampling, by which efficiency and stability of the Monte Carlo simulation is improved. In the proposed method, the hypersphere sampling is developed to autonomously find the optimal shift-vector. The sampling is also limited to the regions where meaningful contribution to the yield is recognized. Simulation examples reveal that the proposed technique stably and efficiently estimates yield of noise stabilities of an SRAM cell. At the failure probability of 10−10, the number of calculation trials has been reduced by six orders magnitude compared with a conventional Monte Carlo simulation.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114355134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450544
V. Honkote, B. Taskin
The square wave generated from the rotary operation with adiabatic switching is a continuously traveling wave, which provides multiple phases of the clock signal on the rotary ring. Recent research in the design automation of rotary clocking implementation has adopted some simplifications of the phase assignments for scalability. Towards this end, the design techniques, employed in conventional IC flows, can be employed for rotary clock automation as well. In this work, a timing framework is developed and skew analysis is presented for the rotary clocking technology to observe the effects of certain design simplifications in timing automation. Further, a methodology is presented to achieve a bounded skew implementation for rotary clocking technology. Experiments performed on R1–R5 benchmark circuits show a negligible increase in wirelength (around 1.25%) for the bounded skew constraint implementation with a 3.5% skew bound, where as, without the bounded skew, overall skew would be 5.5%.
{"title":"Skew analysis and bounded skew constraint methodology for rotary clocking technology","authors":"V. Honkote, B. Taskin","doi":"10.1109/ISQED.2010.5450544","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450544","url":null,"abstract":"The square wave generated from the rotary operation with adiabatic switching is a continuously traveling wave, which provides multiple phases of the clock signal on the rotary ring. Recent research in the design automation of rotary clocking implementation has adopted some simplifications of the phase assignments for scalability. Towards this end, the design techniques, employed in conventional IC flows, can be employed for rotary clock automation as well. In this work, a timing framework is developed and skew analysis is presented for the rotary clocking technology to observe the effects of certain design simplifications in timing automation. Further, a methodology is presented to achieve a bounded skew implementation for rotary clocking technology. Experiments performed on R1–R5 benchmark circuits show a negligible increase in wirelength (around 1.25%) for the bounded skew constraint implementation with a 3.5% skew bound, where as, without the bounded skew, overall skew would be 5.5%.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130112795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450519
S. Yusof, Lau Meng Tee
In today's IC Design, EDA tools are not limited to IC designer's toys. The application of EDA has expanded into a larger scope including generation and extraction of critical information of a design for yield, quality and reliability analysis.
{"title":"Multi-programming environment for structure under pads (SUP) and via arrays pattern recognition automated classification system","authors":"S. Yusof, Lau Meng Tee","doi":"10.1109/ISQED.2010.5450519","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450519","url":null,"abstract":"In today's IC Design, EDA tools are not limited to IC designer's toys. The application of EDA has expanded into a larger scope including generation and extraction of critical information of a design for yield, quality and reliability analysis.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131828054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450526
M. Fujita, H. Tanida, Fei Gao, Tasuku Nishihara, Takeshi Matsumoto
Protocol transducer which realizes translations between multiple protocols is one of the key components in IP-based design methodology. Although there have been researches on automatic synthesis of such protocol transducers, they cannot efficiently deal with out-of-order type communications frequently found in the state-of-the-art protocols. In this paper we present an automatic synthesis method which can deal with complicated state-of-the-art protocols by clearly separating control and datapath parts of the synthesized protocol transducers and introducing four types of configurations in the datapath parts of the protocol transducers. We also present a formal verification method based on inclusion checking between the given protocol transducer to be verified and the all possible protocol transducers which can be generated through our synthesis method. By using simulation-based filtering methods followed by a complete analysis of the entire design and state space, large and complicated protocol transducers can be efficiently and formally verified. Experimental results show their practical usefulness even for protocol transducers for complicated state-of-the-art protocols.
{"title":"Synthesis and formal verification of on-chip protocol transducers through decomposed specification","authors":"M. Fujita, H. Tanida, Fei Gao, Tasuku Nishihara, Takeshi Matsumoto","doi":"10.1109/ISQED.2010.5450526","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450526","url":null,"abstract":"Protocol transducer which realizes translations between multiple protocols is one of the key components in IP-based design methodology. Although there have been researches on automatic synthesis of such protocol transducers, they cannot efficiently deal with out-of-order type communications frequently found in the state-of-the-art protocols. In this paper we present an automatic synthesis method which can deal with complicated state-of-the-art protocols by clearly separating control and datapath parts of the synthesized protocol transducers and introducing four types of configurations in the datapath parts of the protocol transducers. We also present a formal verification method based on inclusion checking between the given protocol transducer to be verified and the all possible protocol transducers which can be generated through our synthesis method. By using simulation-based filtering methods followed by a complete analysis of the entire design and state space, large and complicated protocol transducers can be efficiently and formally verified. Experimental results show their practical usefulness even for protocol transducers for complicated state-of-the-art protocols.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115601317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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