Analysis of First- and Second-Order Digital DS Modulator Used in Fractional-N PLLs

M. Vo
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Abstract

In this paper, we analyze for the first time behavior in the time domain of the accumulated quantization error induced by the first- and second-order digital DeltaSigma modulator (DSM). The DSM is adopted in fractional-N PLLs to dither frequency division factor. From the analysis, difference in behavior of the accumulated quantization error in the two cases is clearly explained. Furthermore, by mean of this, the reason of using second-order DSM is required for the calibration loop of digital/time converter canceling the quantization error is revealed. It also explains why there is variation in convergence time even with the second-order DSM when fractional part of the division factor changes.
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用于分数n锁相环的一阶和二阶数字DS调制器分析
本文分析了一阶和二阶DeltaSigma数字调制器(DSM)引起的累积量化误差在时域上的首次行为。分n锁相环采用DSM来抑制分频因子。通过分析,清楚地解释了两种情况下累积量化误差的行为差异。进而揭示了数字/时间变换器校正回路需要采用二阶DSM来消除量化误差的原因。这也解释了为什么即使是二阶DSM,当分割因子的小数部分发生变化时,收敛时间也会发生变化。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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