A timing synchronizer system for beam test setups requiring galvanic isolation

Abstract

In beam test setups detector elements together with a readout composed of Frontend Electronics and usually an Field-Programmable Gate Array (FPGA) based layer are being analyzed. The frontend electronics is in this scenario often directly connected to both the detector and the FPGA layer what in many cases requires sharing the ground potentials of these layers. This setup can become problematic if parts of the detector need to be operated at different high-voltage potentials, since all of the FPGA boards need to receive a common clock and timing reference in order to synchronize the readout. Thus, for the context of the CBM experiment a versatile Timing Synchronizer system was designed providing galvanically isolated timing distribution links.