Pub Date : 2016-08-15DOI: 10.1109/RTC.2016.7543129
M. Cieslak, K. Gamage
Pulse Shape Discrimination (PSD) algorithms can reliably separate neutrons and gamma-ray photons interacting in a scintillation detector. When implemented in the digital domain, the PSD algorithms allow real-time discrimination between neutron and gamma sources. This paper presents a design of a readout electronics system to retrieve data from a multi-anode photomultiplier tube (MAPMT) for a scintillator based coded-aperture neutron imager. The scintillator is to be coupled with Hamamatsu H9500, a square MAPMT, where each anode of the MAPMT is linked to a resistor network to infer the position of incidence of radiation within the scintillant. Additionally, the resistor network output signals are to be filtered through a novel noise reduction circuit to preserve the data corresponding to each pulse. Localised pulses are digitised using high sampling rate Analogue to Digital Converter (ADC). Sampled signals are temporarily stored in a local ping-pong buffer, before being processed on a field programmable gate array (FPGA). Initial results suggest that 150 MSPS rate provides sufficient information for neutron gamma source discrimination using PSD. Parallel real-time signal processing, implemented on the FPGA, enables multi-channel functioning to generate an array of interactions within the scintillator in terms of gamma rays and neutrons.
{"title":"Design and development of a real-time readout electronics system to retrieve data from a square multi-anode photomultiplier tube for neutron gamma pulse shape discrimination","authors":"M. Cieslak, K. Gamage","doi":"10.1109/RTC.2016.7543129","DOIUrl":"https://doi.org/10.1109/RTC.2016.7543129","url":null,"abstract":"Pulse Shape Discrimination (PSD) algorithms can reliably separate neutrons and gamma-ray photons interacting in a scintillation detector. When implemented in the digital domain, the PSD algorithms allow real-time discrimination between neutron and gamma sources. This paper presents a design of a readout electronics system to retrieve data from a multi-anode photomultiplier tube (MAPMT) for a scintillator based coded-aperture neutron imager. The scintillator is to be coupled with Hamamatsu H9500, a square MAPMT, where each anode of the MAPMT is linked to a resistor network to infer the position of incidence of radiation within the scintillant. Additionally, the resistor network output signals are to be filtered through a novel noise reduction circuit to preserve the data corresponding to each pulse. Localised pulses are digitised using high sampling rate Analogue to Digital Converter (ADC). Sampled signals are temporarily stored in a local ping-pong buffer, before being processed on a field programmable gate array (FPGA). Initial results suggest that 150 MSPS rate provides sufficient information for neutron gamma source discrimination using PSD. Parallel real-time signal processing, implemented on the FPGA, enables multi-channel functioning to generate an array of interactions within the scintillator in terms of gamma rays and neutrons.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125372245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-15DOI: 10.1109/RTC.2016.7543130
Wei Zheng, F. Hu, Ming Zhang, Da Li, Q. Hu, Hai Jin, Yuan Pan
Tearing Modes (TMs) degrade the performance of tokamak plasma, and can even lead to disruption. Using externally exerted resonant magnetic perturbations (RMP) to suppress tearing mode is a promising and effective way. In order to suppress 2/1 tearing mode, 2/1 RMP applied in given phase region to stabilize magnetic island and accelerate island rotation. The RMP feedback control system acquires 15-channels Mirnov poloidal signals, processes the acquired data and calculates the phase in real-time; outputs RMP power supply control signal by comparing with the given phase to drive RMP coil. The feedback control system is based on NI C-RIO and mainly using LabVIEW to develop. The typical 2/1 mode magnetic island on J-TEXT rotates at a frequency from 2 KHz to 10 KHz. To ensure the control precision within 2 degrees, the control period must be within 500 ns. Due to acquired signals are noisy, the feedback control system uses a series of error correction methods in realtime to obtain accurate phase.
{"title":"Real-time resonant magnetic perturbations feedback control system for tearing mode suppression on J-TEXT","authors":"Wei Zheng, F. Hu, Ming Zhang, Da Li, Q. Hu, Hai Jin, Yuan Pan","doi":"10.1109/RTC.2016.7543130","DOIUrl":"https://doi.org/10.1109/RTC.2016.7543130","url":null,"abstract":"Tearing Modes (TMs) degrade the performance of tokamak plasma, and can even lead to disruption. Using externally exerted resonant magnetic perturbations (RMP) to suppress tearing mode is a promising and effective way. In order to suppress 2/1 tearing mode, 2/1 RMP applied in given phase region to stabilize magnetic island and accelerate island rotation. The RMP feedback control system acquires 15-channels Mirnov poloidal signals, processes the acquired data and calculates the phase in real-time; outputs RMP power supply control signal by comparing with the given phase to drive RMP coil. The feedback control system is based on NI C-RIO and mainly using LabVIEW to develop. The typical 2/1 mode magnetic island on J-TEXT rotates at a frequency from 2 KHz to 10 KHz. To ensure the control precision within 2 degrees, the control period must be within 500 ns. Due to acquired signals are noisy, the feedback control system uses a series of error correction methods in realtime to obtain accurate phase.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122317957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-15DOI: 10.1109/RTC.2016.7543128
Woong-ryol Lee, Taegu Lee, Kihyun Kim, P. Milne, G. Kwon, Jaesic Hong
For the systematic standardization of the real time control at Korea Superconducting Tokamak Advanced Research (KSTAR) facility, we developed a new functional digital controller based on the MTCA.4 Standard. The KSTAR Multifunction Control Unit (KMCU, K-Z35) is realized using Xilinx System-On-Chip (SOC) architecture. The KMCU is matched with a dedicated Rear Transition Module (RTM) with sites for two FMC-like analog Data Acquisition (DAQ) modules. The first DAQ system to be implemented is the Motional Stark Effect (MSE) diagnostic. We also implement a two way steaming data transmission function for the real time plasma control. We present the complete data acquisition system and operation results which is configured with MTCA.4 standards.
{"title":"MicroTCA.4 based data acquisition system for KSTAR Tokamak","authors":"Woong-ryol Lee, Taegu Lee, Kihyun Kim, P. Milne, G. Kwon, Jaesic Hong","doi":"10.1109/RTC.2016.7543128","DOIUrl":"https://doi.org/10.1109/RTC.2016.7543128","url":null,"abstract":"For the systematic standardization of the real time control at Korea Superconducting Tokamak Advanced Research (KSTAR) facility, we developed a new functional digital controller based on the MTCA.4 Standard. The KSTAR Multifunction Control Unit (KMCU, K-Z35) is realized using Xilinx System-On-Chip (SOC) architecture. The KMCU is matched with a dedicated Rear Transition Module (RTM) with sites for two FMC-like analog Data Acquisition (DAQ) modules. The first DAQ system to be implemented is the Motional Stark Effect (MSE) diagnostic. We also implement a two way steaming data transmission function for the real time plasma control. We present the complete data acquisition system and operation results which is configured with MTCA.4 standards.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133644281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-15DOI: 10.1109/RTC.2016.7543164
J. Andre, A. Andronidis, U. Behrens, J. Branson, P. Brummer, O. Chaze, C. Contescu, B. G. Craigs, S. Cittolin, G. Darlea, C. Deldicque, Z. Demiragli, M. Dobson, S. Erhan, J. Fulcher, D. Gigi, F. Glege, G. Gomez-Ceballos, J. Hegeman, A. Holzner, Raul Jimenez-Estupianan, L. Masetti, F. Meijers, E. Meschi, R. Mommsen, S. Morović, V. O’dell, L. Orsini, C. Paus, M. Pieri, A. Rácz, H. Sakulin, C. Schwick, T. Reis, D. Simelevicius, P. Zejdl
The data acquisition system (DAQ) of the CMS experiment at the CERN Large Hadron Collider (LHC) assembles events at a rate of 100 kHz, transporting event data at an aggregate throughput of more than 100GB/s to the Highlevel Trigger (HLT) farm. The HLT farm selects and classifies interesting events for storage and offline analysis at an output rate of around 1 kHz. The DAQ system has been redesigned during the accelerator shutdown in 2013-2014. The motivation for this upgrade was twofold. Firstly, the compute nodes, networking and storage infrastructure were reaching the end of their lifetimes. Secondly, in order to maintain physics performance with higher LHC luminosities and increasing event pileup, a number of sub-detectors are being upgraded, increasing the number of readout channels as well as the required throughput, and replacing the off-detector readout electronics with a MicroTCA-based DAQ interface. The new DAQ architecture takes advantage of the latest developments in the computing industry. For data concentration 10/40 Gbit/s Ethernet technologies are used, and a 56Gbit/s Infiniband FDR CLOS network (total throughput ≈ 4Tbit/s) has been chosen for the event builder. The upgraded DAQ - HLT interface is entirely file-based, essentially decoupling the DAQ and HLT systems. The fully-built events are transported to the HLT over 10/40 Gbit/s Ethernet via a network file system. The collection of events accepted by the HLT and the corresponding metadata are buffered on a global file system before being transferred off-site. The monitoring of the HLT farm and the data-taking performance is based on the Elasticsearch analytics tool. This paper presents the requirements, implementation, and performance of the system. Experience is reported on the first year of operation with LHC proton-proton runs as well as with the heavy ion lead-lead runs in 2015.
{"title":"Performance of the new DAQ system of the CMS experiment for run-2","authors":"J. Andre, A. Andronidis, U. Behrens, J. Branson, P. Brummer, O. Chaze, C. Contescu, B. G. Craigs, S. Cittolin, G. Darlea, C. Deldicque, Z. Demiragli, M. Dobson, S. Erhan, J. Fulcher, D. Gigi, F. Glege, G. Gomez-Ceballos, J. Hegeman, A. Holzner, Raul Jimenez-Estupianan, L. Masetti, F. Meijers, E. Meschi, R. Mommsen, S. Morović, V. O’dell, L. Orsini, C. Paus, M. Pieri, A. Rácz, H. Sakulin, C. Schwick, T. Reis, D. Simelevicius, P. Zejdl","doi":"10.1109/RTC.2016.7543164","DOIUrl":"https://doi.org/10.1109/RTC.2016.7543164","url":null,"abstract":"The data acquisition system (DAQ) of the CMS experiment at the CERN Large Hadron Collider (LHC) assembles events at a rate of 100 kHz, transporting event data at an aggregate throughput of more than 100GB/s to the Highlevel Trigger (HLT) farm. The HLT farm selects and classifies interesting events for storage and offline analysis at an output rate of around 1 kHz. The DAQ system has been redesigned during the accelerator shutdown in 2013-2014. The motivation for this upgrade was twofold. Firstly, the compute nodes, networking and storage infrastructure were reaching the end of their lifetimes. Secondly, in order to maintain physics performance with higher LHC luminosities and increasing event pileup, a number of sub-detectors are being upgraded, increasing the number of readout channels as well as the required throughput, and replacing the off-detector readout electronics with a MicroTCA-based DAQ interface. The new DAQ architecture takes advantage of the latest developments in the computing industry. For data concentration 10/40 Gbit/s Ethernet technologies are used, and a 56Gbit/s Infiniband FDR CLOS network (total throughput ≈ 4Tbit/s) has been chosen for the event builder. The upgraded DAQ - HLT interface is entirely file-based, essentially decoupling the DAQ and HLT systems. The fully-built events are transported to the HLT over 10/40 Gbit/s Ethernet via a network file system. The collection of events accepted by the HLT and the corresponding metadata are buffered on a global file system before being transferred off-site. The monitoring of the HLT farm and the data-taking performance is based on the Elasticsearch analytics tool. This paper presents the requirements, implementation, and performance of the system. Experience is reported on the first year of operation with LHC proton-proton runs as well as with the heavy ion lead-lead runs in 2015.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116122363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-15DOI: 10.1109/RTC.2016.7543132
D. Barrientos, J. Molendijk
The Advanced Wakefield Experiment (AWAKE) aims at studying the proton-driven plasma wakefield acceleration technique for the first time. The testing facility, currently being built at CERN, uses the proton beam at a momentum of 400 GeV/c from the Super Proton Synchrotron (SPS) to accelerate an electron beam to the GeV scale over 10 m of plasma. In order to achieve such an acceleration gradient, the reference signal of the low-level RF (LLRF) system controlling the proton beam must keep in-phase with the reference signal used to generate the electron beam and plasma (laser). Even though the SPS LLRF system is located about 3 km away from the laser and electron beam electronics, the phase drift between the three references has been specified to be in the sub-picosecond range. In order to cope with the experiment requirements, we have developed a custom VME board and a digital control system embedded in a FPGA to compensate for the phase drift between the reference signals at both ends of the optical links. In this work, we present the results of the study developed to analyze the expected phase drift, the selected method to compensate it and the performance of the first prototypes of the board. The use of a very precise phase detector and digitally controlled delay lines, both in the level of tens of femtoseconds allow tracking the phase drifts and compensate for them with a very high precision. Measurements of the achieved precision in the developed module have shown to be in the sub-picosecond range, as demanded by the experiment requirements.
{"title":"Phase stabilization over a 3 km optical link with sub-picosecond precision for the AWAKE experiment","authors":"D. Barrientos, J. Molendijk","doi":"10.1109/RTC.2016.7543132","DOIUrl":"https://doi.org/10.1109/RTC.2016.7543132","url":null,"abstract":"The Advanced Wakefield Experiment (AWAKE) aims at studying the proton-driven plasma wakefield acceleration technique for the first time. The testing facility, currently being built at CERN, uses the proton beam at a momentum of 400 GeV/c from the Super Proton Synchrotron (SPS) to accelerate an electron beam to the GeV scale over 10 m of plasma. In order to achieve such an acceleration gradient, the reference signal of the low-level RF (LLRF) system controlling the proton beam must keep in-phase with the reference signal used to generate the electron beam and plasma (laser). Even though the SPS LLRF system is located about 3 km away from the laser and electron beam electronics, the phase drift between the three references has been specified to be in the sub-picosecond range. In order to cope with the experiment requirements, we have developed a custom VME board and a digital control system embedded in a FPGA to compensate for the phase drift between the reference signals at both ends of the optical links. In this work, we present the results of the study developed to analyze the expected phase drift, the selected method to compensate it and the performance of the first prototypes of the board. The use of a very precise phase detector and digitally controlled delay lines, both in the level of tens of femtoseconds allow tracking the phase drifts and compensate for them with a very high precision. Measurements of the achieved precision in the developed module have shown to be in the sub-picosecond range, as demanded by the experiment requirements.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"196 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116216199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-15DOI: 10.1109/RTC.2016.7543114
M. Drochner, H. Kleines, R. Moller, A. Radulescu, M. Delong, D. McCormick
At the “KWS2” small angle scattering instrument at the “FRM-2” neutron source at Garching, Germany a new 3He neutron detector was installed and commissioned in 2015. It is built of 18 “8-pack” modules from GE Power / Reuter-Stokes. Each of these modules has its own data acquisition and slow control processor, using only Gigabit Ethernet as its connection to the outside world. We show how data acquisition, time synchronization and interaction with the slow control system are laid out, as well as some first results and performance data.
2015年，在德国Garching“FRM-2”中子源的“KWS2”小角散射仪上安装了一台新的3He中子探测器并投入使用。它由GE Power / reuters - stokes提供的18个“8包”模块组成。每个模块都有自己的数据采集和慢速控制处理器，仅使用千兆以太网作为与外部世界的连接。我们展示了如何进行数据采集、时间同步和与慢速控制系统的交互，以及一些初步结果和性能数据。
{"title":"Data acquisition and protection system for a multi-MHz neutron detector","authors":"M. Drochner, H. Kleines, R. Moller, A. Radulescu, M. Delong, D. McCormick","doi":"10.1109/RTC.2016.7543114","DOIUrl":"https://doi.org/10.1109/RTC.2016.7543114","url":null,"abstract":"At the “KWS2” small angle scattering instrument at the “FRM-2” neutron source at Garching, Germany a new 3He neutron detector was installed and commissioned in 2015. It is built of 18 “8-pack” modules from GE Power / Reuter-Stokes. Each of these modules has its own data acquisition and slow control processor, using only Gigabit Ethernet as its connection to the outside world. We show how data acquisition, time synchronization and interaction with the slow control system are laid out, as well as some first results and performance data.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124983698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-15DOI: 10.1109/RTC.2016.7543108
D. Pedretti, S. Pavinato, M. Betti, D. Bortolato, F. Gelain, D. Marcato, M. Bellato, R. Isocrate, Matteo Bertocco
SPES is a second generation ISOL radioactive ion beam facility in construction at the INFN National Laboratories of Legnaro (LNL). Its distributed control system embeds custom control in almost all instruments or cluster of homogeneous devices. Nevertheless, standardization is an important issue that concerns modularity and long term maintainability for a facility that has a life span of at least twenty years. In this context, the research project presented in this paper focuses on the design of a custom Input Output Controller (IOC) which acts as a local intelligent node in the distributed control network and is generic enough to perform several different tasks spanning from security and surveillance operations, beam diagnostic, data acquisition and data logging, real-time processing and trigger generation. The IOC exploits the Computer On Module (COM) Express standard that is available in different form factors and processors, fulfilling the computational power requirement of varied applications. The Intel x86_64 architecture makes software development straightforward, easing the portability. The result is a custom motherboard with several application specific features and generic PC functionalities. The design is modular to a certain extent, thanks to an hardware abstraction layer and allows the development of soft and hard real-time applications by means of a real-time Operating System and the on-board FPGA closely coupled to the CPU. Three PCIe slots, a FPGA Mezzanine Card (FMC) connector and several general-purpose digital/analog inputs/outputs enable functionality extensions. An optical fiber link connected to the FPGA is an high speed interface for high throughput data acquisitions or time-sensitive applications. The power distribution complies the AT standard and the whole board can be powered via Power Over Ethernet (POE+) IEEE 802.3at standard. Networking and device-to-cloud connectivity are guaranteed by a gigabit Ethernet link. The design, performance of the prototypes and intended usage will be presented.
SPES是第二代ISOL放射性离子束设备，目前正在意大利莱纳罗国家实验室(LNL)建设中。其分布式控制系统在几乎所有仪器或同质设备集群中嵌入定制控制。然而，标准化是一个重要的问题，它涉及到至少有20年寿命的设施的模块化和长期可维护性。在此背景下，本文提出的研究项目侧重于自定义输入输出控制器(IOC)的设计，该控制器作为分布式控制网络中的本地智能节点，并且足够通用，可以执行从安全和监视操作，波束诊断，数据采集和数据记录，实时处理和触发生成等多个不同的任务。IOC利用计算机模块(COM) Express标准，该标准可用于不同的形状因素和处理器，满足各种应用的计算能力需求。Intel x86_64架构使软件开发变得简单，易于移植。其结果是一个自定义主板与几个应用程序特定的功能和通用的PC功能。该设计在一定程度上是模块化的，由于硬件抽象层，允许通过实时操作系统和板载FPGA与CPU紧密耦合来开发软硬实时应用。三个PCIe插槽，一个FPGA mezz卡(FMC)连接器和几个通用数字/模拟输入/输出支持功能扩展。连接到FPGA的光纤链路是高通量数据采集或时间敏感应用的高速接口。配电符合AT标准，支持POE (power Over Ethernet) IEEE 802.3at全板供电。网络和设备到云的连接由千兆以太网链路保证。将介绍原型机的设计、性能和预期用途。
{"title":"An I/O controller for real time distributed tasks in particle accelerators","authors":"D. Pedretti, S. Pavinato, M. Betti, D. Bortolato, F. Gelain, D. Marcato, M. Bellato, R. Isocrate, Matteo Bertocco","doi":"10.1109/RTC.2016.7543108","DOIUrl":"https://doi.org/10.1109/RTC.2016.7543108","url":null,"abstract":"SPES is a second generation ISOL radioactive ion beam facility in construction at the INFN National Laboratories of Legnaro (LNL). Its distributed control system embeds custom control in almost all instruments or cluster of homogeneous devices. Nevertheless, standardization is an important issue that concerns modularity and long term maintainability for a facility that has a life span of at least twenty years. In this context, the research project presented in this paper focuses on the design of a custom Input Output Controller (IOC) which acts as a local intelligent node in the distributed control network and is generic enough to perform several different tasks spanning from security and surveillance operations, beam diagnostic, data acquisition and data logging, real-time processing and trigger generation. The IOC exploits the Computer On Module (COM) Express standard that is available in different form factors and processors, fulfilling the computational power requirement of varied applications. The Intel x86_64 architecture makes software development straightforward, easing the portability. The result is a custom motherboard with several application specific features and generic PC functionalities. The design is modular to a certain extent, thanks to an hardware abstraction layer and allows the development of soft and hard real-time applications by means of a real-time Operating System and the on-board FPGA closely coupled to the CPU. Three PCIe slots, a FPGA Mezzanine Card (FMC) connector and several general-purpose digital/analog inputs/outputs enable functionality extensions. An optical fiber link connected to the FPGA is an high speed interface for high throughput data acquisitions or time-sensitive applications. The power distribution complies the AT standard and the whole board can be powered via Power Over Ethernet (POE+) IEEE 802.3at standard. Networking and device-to-cloud connectivity are guaranteed by a gigabit Ethernet link. The design, performance of the prototypes and intended usage will be presented.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130610059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-15DOI: 10.1109/RTC.2016.7543162
V. C. Barroso, U. Fuchs, A. Wegrzynek
ALICE (A Large Ion Collider Experiment) is the heavy-ion detector designed to study the physics of strongly interacting matter and the quark-gluon plasma at the CERN LHC (Large Hadron Collider). ALICE has been successfully collecting physics data of Run 2 since spring 2015. In parallel, preparations for a major upgrade, called O2 (Online-Offline) and scheduled for the Long Shutdown 2 in 2019-2020, are being made. One of the major requirements is the capacity to transport data between so-called FLPs (First Level Processors), equipped with readout cards, and the EPNs (Event Processing Node), performing data aggregation, frame building and partial reconstruction. It is foreseen to have 268 FLPs dispatching data to 1500 EPNs with an average output of 20 Gb/s each. In overall, the O2 processing system will operate at terabits per second of throughput while handling millions of concurrent connections. To meet these requirements, the software and hardware layers of the new system need to be fully evaluated. In order to achieve a high performance to cost ratio three networking technologies (Ethernet, InfiniBand and Omni-Path) were benchmarked on Intel and IBM platforms. The core of the new transport layer will be based on a message queue library that supports push-pull and request-reply communication patterns and multipart messages. ZeroMQ and nanomsg are being evaluated as candidates and were tested in detail over the selected network technologies. This paper describes the benchmark programs and setups that were used during the tests, the significance of tuned kernel parameters, the configuration of network driver and the tuning of multi-core, multi-CPU, and NUMA (Non-Uniform Memory Access) architecture. It presents, compares and comments the final results. Eventually, it indicates the most efficient network technology and message queue library pair and provides an evaluation of the needed CPU and memory resources to handle foreseen traffic.
{"title":"Benchmarking message queue libraries and network technologies to transport large data volume in the ALICE O system","authors":"V. C. Barroso, U. Fuchs, A. Wegrzynek","doi":"10.1109/RTC.2016.7543162","DOIUrl":"https://doi.org/10.1109/RTC.2016.7543162","url":null,"abstract":"ALICE (A Large Ion Collider Experiment) is the heavy-ion detector designed to study the physics of strongly interacting matter and the quark-gluon plasma at the CERN LHC (Large Hadron Collider). ALICE has been successfully collecting physics data of Run 2 since spring 2015. In parallel, preparations for a major upgrade, called O2 (Online-Offline) and scheduled for the Long Shutdown 2 in 2019-2020, are being made. One of the major requirements is the capacity to transport data between so-called FLPs (First Level Processors), equipped with readout cards, and the EPNs (Event Processing Node), performing data aggregation, frame building and partial reconstruction. It is foreseen to have 268 FLPs dispatching data to 1500 EPNs with an average output of 20 Gb/s each. In overall, the O2 processing system will operate at terabits per second of throughput while handling millions of concurrent connections. To meet these requirements, the software and hardware layers of the new system need to be fully evaluated. In order to achieve a high performance to cost ratio three networking technologies (Ethernet, InfiniBand and Omni-Path) were benchmarked on Intel and IBM platforms. The core of the new transport layer will be based on a message queue library that supports push-pull and request-reply communication patterns and multipart messages. ZeroMQ and nanomsg are being evaluated as candidates and were tested in detail over the selected network technologies. This paper describes the benchmark programs and setups that were used during the tests, the significance of tuned kernel parameters, the configuration of network driver and the tuning of multi-core, multi-CPU, and NUMA (Non-Uniform Memory Access) architecture. It presents, compares and comments the final results. Eventually, it indicates the most efficient network technology and message queue library pair and provides an evaluation of the needed CPU and memory resources to handle foreseen traffic.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"297 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122978174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-15DOI: 10.1109/RTC.2016.7543181
Li-bo Cheng, F. Anghinolfi, Ke Wang, Hong-Bo Zhu, W. Lu, Zhen-an Liu
As physicists want to put more and more functionalities and algorithms into frontend ASICs, the logic design (of some ASICs) become more and more complicated. A reliable, robust functional verification testbench is one of the most important part during ASIC design. This paper presents a well-constructed testbench based on Universal Verification Methodology(UVM) research for ATLAS Phase-II upgrade silicon strip detector front-end readout chip.
{"title":"A testbench research based on UVM for ABCStar","authors":"Li-bo Cheng, F. Anghinolfi, Ke Wang, Hong-Bo Zhu, W. Lu, Zhen-an Liu","doi":"10.1109/RTC.2016.7543181","DOIUrl":"https://doi.org/10.1109/RTC.2016.7543181","url":null,"abstract":"As physicists want to put more and more functionalities and algorithms into frontend ASICs, the logic design (of some ASICs) become more and more complicated. A reliable, robust functional verification testbench is one of the most important part during ASIC design. This paper presents a well-constructed testbench based on Universal Verification Methodology(UVM) research for ATLAS Phase-II upgrade silicon strip detector front-end readout chip.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127615492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-15DOI: 10.1109/RTC.2016.7543103
Kai Chen
The high-luminosity phase of the Large Hadron Collider (LHC) will provide 5-7 times greater instantaneous and total luminosities than assumed in the original design of the ATLAS Liquid Argon (LAr) Calorimeters and their readout system. The improved trigger system has a higher acceptance rate of 1 MHz and a longer latency of up to 60 micro-seconds. This requires an upgrade of the readout electronics, and a better radiation tolerance is also required. This paper will present concepts for the future readout of the 182,468 calorimeter channels at 40 or 80 MHz with a 16 bit dynamic range. Progress of the development of low-noise, low-power and high-bandwidth electronic components will be presented. These include radiation-tolerant preamplifiers, analog-to-digital converters (ADC) up to 14 bits and low-power optical links providing transfer rates of at least 10 Gbps per fiber.
{"title":"Development of ATLAS Liquid Argon Calorimeters readout electronics for HL-LHC","authors":"Kai Chen","doi":"10.1109/RTC.2016.7543103","DOIUrl":"https://doi.org/10.1109/RTC.2016.7543103","url":null,"abstract":"The high-luminosity phase of the Large Hadron Collider (LHC) will provide 5-7 times greater instantaneous and total luminosities than assumed in the original design of the ATLAS Liquid Argon (LAr) Calorimeters and their readout system. The improved trigger system has a higher acceptance rate of 1 MHz and a longer latency of up to 60 micro-seconds. This requires an upgrade of the readout electronics, and a better radiation tolerance is also required. This paper will present concepts for the future readout of the 182,468 calorimeter channels at 40 or 80 MHz with a 16 bit dynamic range. Progress of the development of low-noise, low-power and high-bandwidth electronic components will be presented. These include radiation-tolerant preamplifiers, analog-to-digital converters (ADC) up to 14 bits and low-power optical links providing transfer rates of at least 10 Gbps per fiber.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"96 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132833138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：