VPN gateways over network processors: implementation and evaluation

Yi-Neng Lin, Chiuan-Hung Lin, Ying-Dar Lin, Y. Lai
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引用次数: 13

Abstract

Networking applications, such as VPN and content filtering, demand extra computing power in order to meet the throughput requirement nowadays. In addition to pure ASIC solutions, network processor architecture is emerging as an alternative to scale up data-plane processing while retaining design flexibility. This article, rather than proposing new algorithms, illustrates the experience in developing IPSec-based VPN gateways over network processors, and investigates the performance issues. The external benchmarks reveal that the system can reach 45 Mbps for IPSec using 3DES algorithm, which improves by 350% compared to single XScale core processor and parallels the throughput of a PIII 1 GHz processor. Through the internal benchmarks, we analyze the turnaround times of the main functional blocks, and identify the core processor as the performance bottleneck for both packet forwarding and IPSec processing.
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基于网络处理器的VPN网关:实现与评估
网络应用,如VPN和内容过滤,需要额外的计算能力,以满足当今的吞吐量需求。除了纯ASIC解决方案之外,网络处理器架构正在成为扩展数据平面处理同时保持设计灵活性的替代方案。本文不是提出新的算法,而是说明了在网络处理器上开发基于ipsec的VPN网关的经验,并研究了性能问题。外部基准测试表明,使用3DES算法的IPSec系统可以达到45 Mbps,与单个XScale核心处理器相比提高了350%,与PIII 1 GHz处理器的吞吐量相当。通过内部基准测试,我们分析了主要功能块的周转时间,并确定了核心处理器是数据包转发和IPSec处理的性能瓶颈。
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