Robustness aspects of 600V GaN-on-Si based power cascoded HFET

D. Veereddy, T. McDonald, J. Ambrus, Alfonso Diy, Stuart Cardwell, Bhargav Pandya, R. Garg, M. Imam
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引用次数: 3

Abstract

The Safe Operating Area (SOA) characteristics of 600 V rated GaN-on-Si based cascode power devices in the Forward Bias (FB) and Short Circuit (SC) test conditions were evaluated in this study. The results from FBSOA tests at ≤ 150 °C device channel temperatures in the linear mode operation demonstrated reliable device operation with negligible parametric drifts. However, the test to destruction FBSOA measurements performed at elevated channel temperatures revealed that the GaN MIS HFET's gate dielectric degradation in the cascode structure is the failure root cause and a theory is presumed to explain the pertinent failure mechanism. Similarly, the destructive SC tests on the cascode GaN devices were conducted that displayed very short withstand times. Through this work, we show that the SC withstand times of GaN devices can be improved by design modifications which come with a Figure of Merit compromise.
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600V GaN-on-Si功率级联fet的鲁棒性
本研究评估了600 V额定GaN-on-Si级联功率器件在正向偏置(FB)和短路(SC)测试条件下的安全工作区域(SOA)特性。线性模式下,FBSOA在≤150°C器件通道温度下的测试结果表明,器件运行可靠,参数漂移可以忽略不计。然而,在高通道温度下进行的FBSOA破坏测试表明,GaN MIS HFET在级联结构中的栅极介电退化是失效的根本原因,并推测了一个理论来解释相关的失效机制。同样,在级联GaN器件上进行了破坏性SC测试,显示出非常短的承受时间。通过这项工作,我们表明,GaN器件的SC承受时间可以通过设计修改来改善,这些设计修改附带了一个优点值妥协。
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