Datapath Optimization for Embedded Signal Processing Architectures utilizing Design Space Exploration

Abstract

According to literature, designers spend up to 30% of the design time on optimizing data representations in signal processing architectures [13]. Reference implementations, mostly in high-level software languages, choose floating point representation for mathematical calculations, which are too resource-intensive for FPGA implementations in many cases. The task of conversion to bit-width-optimized fixed point representations is tedious and therefore warrants automation. Usually some analytical or simulation-based approach is used for this, but past works usually overcomplicate their mode of operation and are therefore not commonplace in FPGA design. In this work, it is shown that a simulation-based approach can be both fast, given modern hardware, as well as simple enough to be integrated into a modern design flow. Using a real-world design from a complex power quality measurement algorithm, this is demonstrated and evaluated. Our implementation was able to reach much better results by reducing the resource utilization by approximately 80%, compared to the bit-widths proposed by a field expert while retaining the accuracy needed for the target application.