Fast fault injection techniques using FPGAs

Abstract

Summary form only given. As manufacturing technology progresses by reducing feature size, providing more integration density and increasing device functionality with lower voltages and more aggressive clock frequencies, the susceptibility to soft errors has grown to an unacceptable level in several application domains. Thus, designers need to assess the needs for soft error mitigation during the design cycle in order to adopt appropriate mitigation strategies. Fault injection is a widely used method to evaluate fault effects and fault tolerance. Fault injection is intended to provide information about fault effects covering several main goals: validate the design under test with respect to reliability requirements; detect weak areas that require error mitigation; and forecast the expected circuit behaviour in the occurrence of faults. In the first case, a typical fault injection approach consists in using a simulation tool to inject and propagate faults in a design model. However, simulation-based fault injection is quite slow. While it can be used to obtain statistical estimations of the soft error susceptibility of a circuit, identifying the critical components of a design is a much more complex task that generally requires huge fault injection campaigns in order to individually assess every component in the circuit. Similarly, huge fault injection campaigns are also required to validate highly protected designs in order to ensure a high fault coverage. In order to accelerate the fault injection process, emulation-based fault injection methods have been developed in recent years. These methods use FPGAs to prototype the circuit under test and support the fault injection mechanisms. This talk will describe recent advances in emulation-based fault injection with FPGAs that can provide unprecedented levels of performance, in the order of millions of faults per second, and support the analysis of Single Event Upset (SEU) and Single-Event Transient (SET) effects on complex circuits. Thanks to this dramatic boost in performance, detailed and accurate evaluations of soft error effects can be obtained to support the adoption of optimal error mitigation strategies. As an illustrative example, emulation-based fault injection enables full characterization of a microprocessor against soft errors on a gate/FF basis for a given workload. Multiple faults, such as Single Event Multiple Upset (SEMU) or Single Event Multiple Transient (SEMT), can also be successfully covered with these methods in an efficient manner.