Advanced Chip Interposer with Micro-Bump Duality

Abstract

Silicon technology and chip design constraints are the main drivers to tile architecture development. In tile architecture, packaged silicon is disaggregated into smaller tiles assembled on a chip interposer, enabling usage of different process node for each tile. This paper describes an advanced 2.5D chip interposer that enables disaggregation using dual micro-bump connectivity. Small geometry, fine pitch micro-bumps, used for die-to-die signals interconnect through the chip interposer. Regular geometry, regular pitch micro-bumps, used for external signals connectivity and power delivery. Majority of regular pitch micro-bumps, use straight through vertical path connection to the package bumps. On a need basis, chip interposer die is used for redistribution routing to package bumps.