Improved digital watermarking method and realization based on FPGA

Abstract

This paper presents a new digital watermarking method, which majors improvement method realised based on single-chip FPGA. The procedure includes dividing the input digital image by block, block selection, sorting the pixel values within the blocks. The data is embedded by using new difference and new histogram-modification-strategy. The definition of new difference takes the position of maximum and the second large value pixel into account. Which is help for to the blocks, in which maximum value equal to the second largest. This algorithm can use these pixel blocks to embed data in. The key algorithm is based on the FPGA, using Verilog HDL language and graphical input method to design on the Quartus II 13.0 software platform. And the processed pixel value will be passed to the computer, providing experimental data for analysis and comparative.