Time Sharing Based Parallel Implementation of CNN on Low Cost FPGA

Shefa A. Dawwd, Basil Sh. Mahmood
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引用次数: 1

Abstract

Convolutional neural network (CNN) is a multilayer architecture, and considered as a robust model for image recognition. Learning in this neural network achieves progressively in its successive layers such that the layers produce higher-level features and the categories are produced by the last layer. To use the CNN in different real time applications, high performance implementation is required. To reduce the resources required for implementation, in this paper a time sharing based parallel implementation of CNN is proposed. The computing of the upper convolution nodes is done sequentially while the parallelism is increased in the direction of the preceding layer resulting maximum parallelism in the bottom layer Then the CNN relatively complex design is implemented on an FPGA model with no more than 200,000 gates and can speed up computation up to 166 times.
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基于时间共享的低成本FPGA CNN并行实现
卷积神经网络(CNN)是一种多层结构,被认为是一种鲁棒的图像识别模型。该神经网络的学习在其连续的层中逐步实现,使得层产生更高级别的特征,而类别由最后一层产生。为了在不同的实时应用中使用CNN,需要高性能的实现。为了减少实现所需的资源,本文提出了一种基于分时的CNN并行实现方法。上层卷积节点的计算按顺序进行,同时沿前一层的方向增加并行度,使底层并行度最大,然后在不超过20万个门的FPGA模型上实现CNN相对复杂的设计,计算速度可提高166倍。
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