High-speed low-power logic gates using floating gates

Abstract

Low power consumption is attractive because of portability and reliability considerations. One way to reduce this power consumption is lowering the supply voltage. However, low supply voltages leads to reduced time performance if the transistor threshold voltage is not scaled accordingly. To solve this, technologies with reduced threshold voltage devices have emerged. Instead, in this paper we resort to a circuit technique based on floating gate devices in order to lower the threshold voltage. It allows fast operation of logic gates at a low supply voltage in standard technologies. The feasibility of the proposed technique is shown experimentally by a fabricated test chip working at a supply voltage of 0.4 V.