Pub Date : 2002-09-01DOI: 10.1109/ISCAS.2002.1009960
Kam-Fai Chan Alton, Kam-Tim Woo, C. Kok
A vector quantization fast search algorithm using a hyperplane based k-dimensional multi-node search tree is presented. The misclassification problem associated with hyperplane decision is eliminated by a multi-level backtracking algorithm. The vector quantization complexity is further lowered by a novel relative distance quantization rule. Triangular inequality is applied to lower bound the search distance, thus eliminating all the sub-trees in the k-dimensional search tree during backtracking. Vector quantization image coding results are presented which show the proposed vector quantization algorithm outperforms other vector quantization algorithms in the literature both in PSNR and computation time.
{"title":"Vector quantization fast search algorithm using hyperplane based k-dimensional multi-node search tree","authors":"Kam-Fai Chan Alton, Kam-Tim Woo, C. Kok","doi":"10.1109/ISCAS.2002.1009960","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1009960","url":null,"abstract":"A vector quantization fast search algorithm using a hyperplane based k-dimensional multi-node search tree is presented. The misclassification problem associated with hyperplane decision is eliminated by a multi-level backtracking algorithm. The vector quantization complexity is further lowered by a novel relative distance quantization rule. Triangular inequality is applied to lower bound the search distance, thus eliminating all the sub-trees in the k-dimensional search tree during backtracking. Vector quantization image coding results are presented which show the proposed vector quantization algorithm outperforms other vector quantization algorithms in the literature both in PSNR and computation time.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129198019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1009838
J. Ramírez-Angulo, A. Torralba, R. Carvajal
Two low-voltage continuous-time schemes are analyzed. They are based on signal dependent floating voltage sources that maintain the op-amp input terminals very close to one of the supply rails. The analysis presented shows that both schemes can operate with single supply voltages lower than 1 V in current CMOS technology.
{"title":"Comparison of two schemes for continuous-time sub-volt op-amp operation","authors":"J. Ramírez-Angulo, A. Torralba, R. Carvajal","doi":"10.1109/ISCAS.2002.1009838","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1009838","url":null,"abstract":"Two low-voltage continuous-time schemes are analyzed. They are based on signal dependent floating voltage sources that maintain the op-amp input terminals very close to one of the supply rails. The analysis presented shows that both schemes can operate with single supply voltages lower than 1 V in current CMOS technology.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"256 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115280997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1009976
M. Hayajneh, A. Scaglione
To quantify the diversity gain of space-time coding, obtained by increasing the number of transmit and receive antennas, in this paper we use the paradigm of random codes, modelling space-time codes as random matrices with zero mean, equal variance and independent entries having a common arbitrary distribution (discrete or continuous). This framework is especially convenient in this situation because: (i) optimal codes are difficult to identify and, thus, are difficult to test; (ii) the eigenvalues of this type of large matrix converge to a specific distribution, mostly known as the semicircle or circle law. This last observation allows us to derive closed form asymptotic expressions for the probability of error in Rayleigh and Rician fading that can be used to gain insight on how the fading and the number of antennas affect the system performance.
{"title":"Space-time codes for high bit rate wireless communications: asymptotic performance of space-time random codes","authors":"M. Hayajneh, A. Scaglione","doi":"10.1109/ISCAS.2002.1009976","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1009976","url":null,"abstract":"To quantify the diversity gain of space-time coding, obtained by increasing the number of transmit and receive antennas, in this paper we use the paradigm of random codes, modelling space-time codes as random matrices with zero mean, equal variance and independent entries having a common arbitrary distribution (discrete or continuous). This framework is especially convenient in this situation because: (i) optimal codes are difficult to identify and, thus, are difficult to test; (ii) the eigenvalues of this type of large matrix converge to a specific distribution, mostly known as the semicircle or circle law. This last observation allows us to derive closed form asymptotic expressions for the probability of error in Rayleigh and Rician fading that can be used to gain insight on how the fading and the number of antennas affect the system performance.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115435886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010659
M. Yagi, T. Shibata
An associative-processor-based VLSI system architecture has been developed for robust grayscale image recognition. The system receives a 64/spl times/64 pels block of a gray scale image, extracting a feature vector from the image and recognizing the image by template matching. An analog associative processor is adopted as the template matching core because it features compact implementation as well as fast processing due to its fully parallel architecture. For generating feature vectors, dedicated digital CMOS circuits have been developed because of their versatility in the algorithm. The analysis of medical X-ray pictures (Cephalometric landmark identification by expert dentists) was taken as an exercise for the system, and intensive computer simulations have been conducted to optimize the recognition performance of the system. Although the entire system has not yet been implemented on a single chip, all the key sub circuits in the system were fabricated as test circuits and their correct functioning has been experimentally demonstrated. It is also shown by experiment that very low power operation of the template matching core is possible by operating the analog circuitry in the subthreshold regime without degrading recognition performance.
{"title":"An associative-processor-based mixed signal system for robust grayscale image recognition","authors":"M. Yagi, T. Shibata","doi":"10.1109/ISCAS.2002.1010659","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010659","url":null,"abstract":"An associative-processor-based VLSI system architecture has been developed for robust grayscale image recognition. The system receives a 64/spl times/64 pels block of a gray scale image, extracting a feature vector from the image and recognizing the image by template matching. An analog associative processor is adopted as the template matching core because it features compact implementation as well as fast processing due to its fully parallel architecture. For generating feature vectors, dedicated digital CMOS circuits have been developed because of their versatility in the algorithm. The analysis of medical X-ray pictures (Cephalometric landmark identification by expert dentists) was taken as an exercise for the system, and intensive computer simulations have been conducted to optimize the recognition performance of the system. Although the entire system has not yet been implemented on a single chip, all the key sub circuits in the system were fabricated as test circuits and their correct functioning has been experimentally demonstrated. It is also shown by experiment that very low power operation of the template matching core is possible by operating the analog circuitry in the subthreshold regime without degrading recognition performance.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115679002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010988
Tzu-Ming Liu, B. Shieh, Chen-Yi Lee
In this paper, the efficient modeling codec architecture for binary shape coding is presented. This novel design includes a memory unit that employs the address generation module and the select-and-barrel shift module to speed up the process of border pixels generation. A simple architecture of the modified modeling unit, which uses a column-scan map to reduce the number of mux and barrel shifters is proposed. Based on the proposed architecture, it deals not only with context computation of the intra mode but also of the inter mode on the same hardware architecture. In addition, this design technique is suitable for the context-based arithmetic encode/decode in the whole MPEG-4 codec system.
{"title":"An efficient modeling codec architecture for binary shape coding","authors":"Tzu-Ming Liu, B. Shieh, Chen-Yi Lee","doi":"10.1109/ISCAS.2002.1010988","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010988","url":null,"abstract":"In this paper, the efficient modeling codec architecture for binary shape coding is presented. This novel design includes a memory unit that employs the address generation module and the select-and-barrel shift module to speed up the process of border pixels generation. A simple architecture of the modified modeling unit, which uses a column-scan map to reduce the number of mux and barrel shifters is proposed. Based on the proposed architecture, it deals not only with context computation of the intra mode but also of the inter mode on the same hardware architecture. In addition, this design technique is suitable for the context-based arithmetic encode/decode in the whole MPEG-4 codec system.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123041911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010490
A. Worapishet, R. Sitdhikorn, J. Hughes
The development of switched-current (SI) complex bandpass filters targeted for radio receiver applications is described in this paper. A filter architecture well suited for SI realisation is introduced followed by the development of the cascoded class AB SI technique to allow high precision in the implemented filter. A verification is given via the design and simulation of a 5th-order 1 MHz centre frequency and bandwidth complex SI bandpass filter with 13 MHz sampling frequency. Operating at 1.8 V supply, the resulting circuit offers precise passband response, less than -54.7 dB and -77 dB in-band and out-band intermodulation, respectively, with 4.9 mW power consumption.
{"title":"Low-power complex channel filtering using cascoded class AB switched-currents","authors":"A. Worapishet, R. Sitdhikorn, J. Hughes","doi":"10.1109/ISCAS.2002.1010490","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010490","url":null,"abstract":"The development of switched-current (SI) complex bandpass filters targeted for radio receiver applications is described in this paper. A filter architecture well suited for SI realisation is introduced followed by the development of the cascoded class AB SI technique to allow high precision in the implemented filter. A verification is given via the design and simulation of a 5th-order 1 MHz centre frequency and bandwidth complex SI bandpass filter with 13 MHz sampling frequency. Operating at 1.8 V supply, the resulting circuit offers precise passband response, less than -54.7 dB and -77 dB in-band and out-band intermodulation, respectively, with 4.9 mW power consumption.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116663631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1009829
Kiyong Choi, D. Allstot, S. Kiaei
Parasitic-aware synthesis and optimization techniques are presented for a 0.35 /spl mu/m CMOS three-stage 1 W 900 MHz class-E power amplifier. Employing bond wire and spiral inductors, it achieves 25 dB gain with 49% drain efficiency from a 3.3 V supply. Simulated annealing optimization is used taking advantage of its ability to escape local minima.
{"title":"Parasitic-aware synthesis of RF CMOS switching power amplifiers","authors":"Kiyong Choi, D. Allstot, S. Kiaei","doi":"10.1109/ISCAS.2002.1009829","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1009829","url":null,"abstract":"Parasitic-aware synthesis and optimization techniques are presented for a 0.35 /spl mu/m CMOS three-stage 1 W 900 MHz class-E power amplifier. Employing bond wire and spiral inductors, it achieves 25 dB gain with 49% drain efficiency from a 3.3 V supply. Simulated annealing optimization is used taking advantage of its ability to escape local minima.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"53 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116863443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010657
Lingfeng Li, D. Gong, Yun He
In this paper, we describe a cost-efficient programmable video signal processor (PVSP) to implement various video encoding and decoding schemes. Hierarchical (two level) programmable control architecture, flexible memory address mapping strategies and a programmable VLC/VLD module are applied in order to achieve sufficient programmability. Thus, PVSP can support various video compression algorithms and standards, such as MPEG-1, MPEG-2 H.263, and MPEG-4. Meanwhile, to improve the throughput of this codec system, some paralleling approaches are exploited on different levels, which include pipeline, tree adder, and SIMD (single instruction stream, multiple data streams). PVSP is estimated to have approximately 320 k gates and it can accomplish MPEG-2 MP@ML encoding in real-time at a frequency of 133 MHz.
{"title":"A single-chip real-time programmable video signal processor","authors":"Lingfeng Li, D. Gong, Yun He","doi":"10.1109/ISCAS.2002.1010657","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010657","url":null,"abstract":"In this paper, we describe a cost-efficient programmable video signal processor (PVSP) to implement various video encoding and decoding schemes. Hierarchical (two level) programmable control architecture, flexible memory address mapping strategies and a programmable VLC/VLD module are applied in order to achieve sufficient programmability. Thus, PVSP can support various video compression algorithms and standards, such as MPEG-1, MPEG-2 H.263, and MPEG-4. Meanwhile, to improve the throughput of this codec system, some paralleling approaches are exploited on different levels, which include pipeline, tree adder, and SIMD (single instruction stream, multiple data streams). PVSP is estimated to have approximately 320 k gates and it can accomplish MPEG-2 MP@ML encoding in real-time at a frequency of 133 MHz.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116874886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1010699
S. Shiraishi, M. Haseyama, H. Kitajima
This paper presents a CORDIC-based architecture for adaptive lattice filters. The proposed filter architecture consists of simple components: a CORDIC processor and an adder, so that it can be implemented with a reduced amount of hardware. Moreover, the proposed architecture is useful for ASIC design because it has a regular, modular, and locally-connected structure. In addition, since our architecture is effective even in case of ARMA lattice filters, it can be utilized for many applications in the digital signal processing field.
{"title":"A cost-effective and high-precision architecture for CORDIC-based adaptive lattice filters","authors":"S. Shiraishi, M. Haseyama, H. Kitajima","doi":"10.1109/ISCAS.2002.1010699","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1010699","url":null,"abstract":"This paper presents a CORDIC-based architecture for adaptive lattice filters. The proposed filter architecture consists of simple components: a CORDIC processor and an adder, so that it can be implemented with a reduced amount of hardware. Moreover, the proposed architecture is useful for ASIC design because it has a regular, modular, and locally-connected structure. In addition, since our architecture is effective even in case of ARMA lattice filters, it can be utilized for many applications in the digital signal processing field.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117137946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISCAS.2002.1011431
N. A. Fraser, B. Nowrouzian
It is well known that /spl Sigma/-/spl Delta/ A/D converters having complementary signal and noise transfer functions exhibit high signal-to-quantization-noise ratios (SQNRs) and high dynamic ranges (DRs), but that they tend to be overly sensitive to capacitor mismatches (potentially leading to unstable converter operation) in a corresponding switched-capacitor (SC) hardware implementation. Recently, a new class of /spl Sigma/-/spl Delta/ A/D converters was developed based on magnitude-squared or magnitude complementary signal and noise transfer functions to decrease the sensitivity to capacitor mismatches at the expense of slightly lower SQNRs and DRs. This paper is concerned with the development of a novel approach to the design of /spl Sigma/-/spl Delta/ A/D converters. This approach combines the transfer function complementarity (in the overall frequency band) with signal and noise transfer function magnitude complementarity (in the signal passband) to obtain a single /spl Sigma/-/spl Delta/ A/D converter with a cascade-of-resonators configuration. Consequently, the resulting A/D converters achieve not only high-stability (arising from magnitude complementarity), but also high DR and SQNR (arising from transfer function complementarity) in the SC hardware implementation. A practical application example is given to illustrate the results.
{"title":"A new approach to the design of low-sensitivity high-resolution bandpass /spl Sigma/-/spl Delta/ A/D converters","authors":"N. A. Fraser, B. Nowrouzian","doi":"10.1109/ISCAS.2002.1011431","DOIUrl":"https://doi.org/10.1109/ISCAS.2002.1011431","url":null,"abstract":"It is well known that /spl Sigma/-/spl Delta/ A/D converters having complementary signal and noise transfer functions exhibit high signal-to-quantization-noise ratios (SQNRs) and high dynamic ranges (DRs), but that they tend to be overly sensitive to capacitor mismatches (potentially leading to unstable converter operation) in a corresponding switched-capacitor (SC) hardware implementation. Recently, a new class of /spl Sigma/-/spl Delta/ A/D converters was developed based on magnitude-squared or magnitude complementary signal and noise transfer functions to decrease the sensitivity to capacitor mismatches at the expense of slightly lower SQNRs and DRs. This paper is concerned with the development of a novel approach to the design of /spl Sigma/-/spl Delta/ A/D converters. This approach combines the transfer function complementarity (in the overall frequency band) with signal and noise transfer function magnitude complementarity (in the signal passband) to obtain a single /spl Sigma/-/spl Delta/ A/D converter with a cascade-of-resonators configuration. Consequently, the resulting A/D converters achieve not only high-stability (arising from magnitude complementarity), but also high DR and SQNR (arising from transfer function complementarity) in the SC hardware implementation. A practical application example is given to illustrate the results.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117160589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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