A 19.1-dBm fully-integrated 24 GHz power amplifier using 0.18-μm CMOS technology

Jing-Lin Kuo, Zuo‐Min Tsai, Huei Wang
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引用次数: 5

Abstract

A 24 GHz, 19.1 dBm fully-integrated power amplifiers (PA) was designed and fabricated in the 0.18-mum deep n-well (DNW) CMOS technology. This power amplifier is a 2-stage design using cascode RF NMOS configuration and has a maximum measured output power of 19.1 dBm, an OP1dB of 13.3 dBm, a power added efficiency (PAE) of 15.6%, and a linear gain of 18.8 dB when VDD and DNW are both biased at 3.6 V. The chip size is only 0.56 times 0.58 mm2. To the authorpsilas knowledge, this PA demonstrates the highest output power of +19.1 dBm among the reported PAs above 15 GHz in CMOS processes.
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采用0.18 μm CMOS技术的19.1 dbm全集成24ghz功率放大器
采用0.18 μ m深n阱(DNW) CMOS技术,设计并制造了一款24 GHz、19.1 dBm的全集成功率放大器(PA)。该功率放大器采用级联RF NMOS配置,最大测量输出功率为19.1 dBm, OP1dB为13.3 dBm,功率附加效率(PAE)为15.6%,当VDD和DNW均偏置在3.6 V时,线性增益为18.8 dB。芯片尺寸仅为0.56 × 0.58 mm2。据作者所知,在CMOS工艺中报道的15 GHz以上的PA中,该PA的最高输出功率为+19.1 dBm。
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