{"title":"GT-EP: a novel high-performance real-time architecture","authors":"W. Tan, H. Russ, C. Alford","doi":"10.1109/ISCA.1991.1021595","DOIUrl":null,"url":null,"abstract":"This paperpresen ts thedesignanddevelopmentof anovelprocess01 architecture targeted forhighperformancereakime applications.Theprocessorconsists of four primary components: inputdevices. output devices, a dataflow processing unit (DPU). and a dataflow control unit (DCU). The central element of the processor is the DPU which consumes data from input devices and produces data to output devices. The flow of data for the DPU is orchestrated by the DCU. Implemented in three silicon<ompiled VLSI chips (one for the DPU and two for the DCU). the design utilizes modem. advanced camputer design concepts and principles to formulate a novel architecture crafted for the target applications. This processor is designated as the \"Executive Processor\" or GT-EP.' Index tams: real-time processing, cornputer architecture, performance constraints. VLSI design, silicon compiler design, dataflow architecture","PeriodicalId":187095,"journal":{"name":"[1991] Proceedings. The 18th Annual International Symposium on Computer Architecture","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1991] Proceedings. The 18th Annual International Symposium on Computer Architecture","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCA.1991.1021595","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
This paperpresen ts thedesignanddevelopmentof anovelprocess01 architecture targeted forhighperformancereakime applications.Theprocessorconsists of four primary components: inputdevices. output devices, a dataflow processing unit (DPU). and a dataflow control unit (DCU). The central element of the processor is the DPU which consumes data from input devices and produces data to output devices. The flow of data for the DPU is orchestrated by the DCU. Implemented in three silicon