A High-Performance Hybrid Full Adder Circuit

Abstract

This research presents a novel hybrid complementary metal oxide semiconductor (CMOS) design for a 1-bit complete adder. The investigation of the hybrid-CMOS design style was prompted by the search for good drivability, low-energy, and noise-robustness operation for deep submicron. Various CMOS logic style circuits are used in hybrid-CMOS design style to design a novel design of full adders with desired performance. This dramatically reduces design efforts by giving designers more freedom to focus on various applications. This work implements a novel full adder design using the FinFET 16 nm technology. At first, an XOR-XNOR circuit is presented that concurrently generates the XOR-XNOR full swing outputs, which is used to implement the full adder. The proposed design reports 23.64% to 74.95% and 13.47% to 81.31 % improvement in power delay product (PDP) and energy-delay product (EDP), respectively, over existing adders.