{"title":"A SOI LDMOS/CMOS/BJT technology for fully-integrated RF power amplifiers","authors":"Y. Tan, M. Kumar, J. Sin, L. Shi, J. Lau","doi":"10.1109/ISPSD.2000.856790","DOIUrl":null,"url":null,"abstract":"This paper describes a SOI LDMOS/CMOS/BJT technology which can be used in portable wireless communication applications. This technology allows the complete integration of the front-end and baseband circuits for low-cost/low-power/high-volume single-chip transceiver implementation. The LDMOS transistors (0.35 /spl mu/m channel length, 3.8 /spl mu/m drift length, 4.5 GHz f/sub T/ and 20 V breakdown voltage), CMOS transistors (1.5 /spl mu/m channel length, 0.8/-1.2V threshold voltage), lateral NPN transistor (18 V BV/sub CBO/ and h/sub FE/ of 20), and high Q-factor (up to 6.1 at 900 MHz and 6.5 at 1.8 GHz) on-chip inductors are fabricated. A fully-functional high performance integrated power amplifier for 900 MHz wireless transceiver application is also demonstrated.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.2000.856790","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
This paper describes a SOI LDMOS/CMOS/BJT technology which can be used in portable wireless communication applications. This technology allows the complete integration of the front-end and baseband circuits for low-cost/low-power/high-volume single-chip transceiver implementation. The LDMOS transistors (0.35 /spl mu/m channel length, 3.8 /spl mu/m drift length, 4.5 GHz f/sub T/ and 20 V breakdown voltage), CMOS transistors (1.5 /spl mu/m channel length, 0.8/-1.2V threshold voltage), lateral NPN transistor (18 V BV/sub CBO/ and h/sub FE/ of 20), and high Q-factor (up to 6.1 at 900 MHz and 6.5 at 1.8 GHz) on-chip inductors are fabricated. A fully-functional high performance integrated power amplifier for 900 MHz wireless transceiver application is also demonstrated.