A SOI LDMOS/CMOS/BJT technology for fully-integrated RF power amplifiers

Y. Tan, M. Kumar, J. Sin, L. Shi, J. Lau
{"title":"A SOI LDMOS/CMOS/BJT technology for fully-integrated RF power amplifiers","authors":"Y. Tan, M. Kumar, J. Sin, L. Shi, J. Lau","doi":"10.1109/ISPSD.2000.856790","DOIUrl":null,"url":null,"abstract":"This paper describes a SOI LDMOS/CMOS/BJT technology which can be used in portable wireless communication applications. This technology allows the complete integration of the front-end and baseband circuits for low-cost/low-power/high-volume single-chip transceiver implementation. The LDMOS transistors (0.35 /spl mu/m channel length, 3.8 /spl mu/m drift length, 4.5 GHz f/sub T/ and 20 V breakdown voltage), CMOS transistors (1.5 /spl mu/m channel length, 0.8/-1.2V threshold voltage), lateral NPN transistor (18 V BV/sub CBO/ and h/sub FE/ of 20), and high Q-factor (up to 6.1 at 900 MHz and 6.5 at 1.8 GHz) on-chip inductors are fabricated. A fully-functional high performance integrated power amplifier for 900 MHz wireless transceiver application is also demonstrated.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.2000.856790","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4

Abstract

This paper describes a SOI LDMOS/CMOS/BJT technology which can be used in portable wireless communication applications. This technology allows the complete integration of the front-end and baseband circuits for low-cost/low-power/high-volume single-chip transceiver implementation. The LDMOS transistors (0.35 /spl mu/m channel length, 3.8 /spl mu/m drift length, 4.5 GHz f/sub T/ and 20 V breakdown voltage), CMOS transistors (1.5 /spl mu/m channel length, 0.8/-1.2V threshold voltage), lateral NPN transistor (18 V BV/sub CBO/ and h/sub FE/ of 20), and high Q-factor (up to 6.1 at 900 MHz and 6.5 at 1.8 GHz) on-chip inductors are fabricated. A fully-functional high performance integrated power amplifier for 900 MHz wireless transceiver application is also demonstrated.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
用于全集成射频功率放大器的SOI LDMOS/CMOS/BJT技术
本文介绍了一种可用于便携式无线通信的SOI LDMOS/CMOS/BJT技术。该技术允许前端和基带电路的完全集成,以实现低成本/低功耗/大容量的单芯片收发器。制作了LDMOS晶体管(通道长度0.35 /spl μ m,漂移长度3.8 /spl μ m, 4.5 GHz f/sub T/和20 V击穿电压)、CMOS晶体管(通道长度1.5 /spl μ m,阈值电压0.8/-1.2V)、横向NPN晶体管(18 V BV/sub CBO/和h/sub FE/为20)和高q因子(900 MHz时高达6.1,1.8 GHz时高达6.5)片上电感。还演示了一种用于900 MHz无线收发器的全功能高性能集成功率放大器。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Complementary LDMOS transistors for a CMOS/BiCMOS process Using "Adaptive resurf" to improve the SOA of LDMOS transistors Evaluation of 600 V/100 A NPT-IGBT with a non-self-align shallow p-well formation techniques A novel free wheeling diode for 1700 V IGBT module Low voltage CMOS compatible power MOSFET for on-chip DC/DC converters
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1