{"title":"A lossless index coding algorithm and VLSI design for vector quantization","authors":"M. Sheu, Sh-Chi Tsai, Ming-Der Shieh","doi":"10.1109/APASIC.1999.824062","DOIUrl":null,"url":null,"abstract":"This paper presents a switching-tree coding (STC) algorithm to re-encode the output codevector indexes after vector quantization. Based on the connections in the index neighborhood, we construct three binary trees to allocate the optimal variable-length noiseless code for each index. Simulation results indicate that this algorithm can improve coding efficiency without introducing any extra coding distortion, as compared to conventional memoryless VQ. Besides, according the new algorithm, an efficient VLSI architecture is also derived under the requirements of low cost and high performance. The gate counts of encoder and decoder are about 5000 and 4800 respectively. After Verilog simulation, the clock rate of the whole architecture is 50 MHz by using 0.6 /spl mu/m CMOS IP3M technology.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APASIC.1999.824062","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 12
Abstract
This paper presents a switching-tree coding (STC) algorithm to re-encode the output codevector indexes after vector quantization. Based on the connections in the index neighborhood, we construct three binary trees to allocate the optimal variable-length noiseless code for each index. Simulation results indicate that this algorithm can improve coding efficiency without introducing any extra coding distortion, as compared to conventional memoryless VQ. Besides, according the new algorithm, an efficient VLSI architecture is also derived under the requirements of low cost and high performance. The gate counts of encoder and decoder are about 5000 and 4800 respectively. After Verilog simulation, the clock rate of the whole architecture is 50 MHz by using 0.6 /spl mu/m CMOS IP3M technology.