Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824020
Kwangoh Kim, Jungryoul Choi, Joongho Choi
This paper describes design of 250 Mbps 10-channel CMOS optical receiver array for computer communication using the general-purpose CMOS technology. It is one of the most important building blocks for parallel optical interconnection system. The receiver array consists of the photo-detectors, amplifier chains and phase-locked loop for data recovery. The chip was fabricated in a 0.65 /spl mu/m 2-poly, 2-metal CMOS technology and dissipates 330 mW for one-channel and 70 mW for PLL for /spl plusmn/2.5 v supply.
{"title":"Design of 250 Mb/s 10-channel CMOS optical receiver array for computer communication","authors":"Kwangoh Kim, Jungryoul Choi, Joongho Choi","doi":"10.1109/APASIC.1999.824020","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824020","url":null,"abstract":"This paper describes design of 250 Mbps 10-channel CMOS optical receiver array for computer communication using the general-purpose CMOS technology. It is one of the most important building blocks for parallel optical interconnection system. The receiver array consists of the photo-detectors, amplifier chains and phase-locked loop for data recovery. The chip was fabricated in a 0.65 /spl mu/m 2-poly, 2-metal CMOS technology and dissipates 330 mW for one-channel and 70 mW for PLL for /spl plusmn/2.5 v supply.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116771179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824013
Young-Hwan Uun, Ho-Jung Yoo, S. Ham, Young-Jun Kim, Yong-hee Lee
Recently, electromagnetic interference (EMI) and radiated emission have become a major problem for high speed circuit and package designers, Most of them are due to power and ground fluctuation. Decoupling capacitors have been mostly used to reduce the power/ground bounce of high-speed digital systems and boards. In this paper, we present a more powerful circuit model for power and ground bounce. This circuit reduces the power and ground bounce by the way of suppressing voltage increase through the resistance which varies with power fluctuation. We present numerical analysis and simulation data by comparing decoupling capacitors.
{"title":"A filter for low EMI and low noise","authors":"Young-Hwan Uun, Ho-Jung Yoo, S. Ham, Young-Jun Kim, Yong-hee Lee","doi":"10.1109/APASIC.1999.824013","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824013","url":null,"abstract":"Recently, electromagnetic interference (EMI) and radiated emission have become a major problem for high speed circuit and package designers, Most of them are due to power and ground fluctuation. Decoupling capacitors have been mostly used to reduce the power/ground bounce of high-speed digital systems and boards. In this paper, we present a more powerful circuit model for power and ground bounce. This circuit reduces the power and ground bounce by the way of suppressing voltage increase through the resistance which varies with power fluctuation. We present numerical analysis and simulation data by comparing decoupling capacitors.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126170624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824044
W. F. Lee, P. Chan, L. Siek, M. C. Yee, S. Y. Chui
Cost and reliability are major considerations in automobile industrial products. These serve as the key driving forces to design low-cost digital-controlled accelerometer interfaces. This paper proposes a cost-effective capacitive accelerometer interface ASIC that adopts ASM methodology to implement an application-specific digital controller for automobile applications. The ASM approach has the advantages over other digital techniques in terms of self-documentation and easy of design. In addition, a new way of independent self-testing of the capacitive accelerometer that is based on inherent slow mechanical response time of the acceleration sensor is presented.
{"title":"An ASM-based ASIC for automobile accelerometer applications","authors":"W. F. Lee, P. Chan, L. Siek, M. C. Yee, S. Y. Chui","doi":"10.1109/APASIC.1999.824044","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824044","url":null,"abstract":"Cost and reliability are major considerations in automobile industrial products. These serve as the key driving forces to design low-cost digital-controlled accelerometer interfaces. This paper proposes a cost-effective capacitive accelerometer interface ASIC that adopts ASM methodology to implement an application-specific digital controller for automobile applications. The ASM approach has the advantages over other digital techniques in terms of self-documentation and easy of design. In addition, a new way of independent self-testing of the capacitive accelerometer that is based on inherent slow mechanical response time of the acceleration sensor is presented.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115568885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824019
Chan Kim, J. Jun, Sang Ho Lee, Jae Geun Kim
In ASIC development, effective simulation leads into functionally more reliable chips as well as faster development time. This paper describes the design and the simulation techniques used in 3 ATM ASIC developments in ETRI. The three ASICs described are: ASAH-NIC-a 155 Mbps ATM SAR chip with internal PCI interface and SDH framer; ASAPI-L4-a 622 Mbps bidirectional ATM layer processing chip with UPC, OAM, QOS buffering capabilities; and ASAH-P4-a 622 Mbps ATM physical layer chip.
{"title":"Design and simulation of three ATM ASICs","authors":"Chan Kim, J. Jun, Sang Ho Lee, Jae Geun Kim","doi":"10.1109/APASIC.1999.824019","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824019","url":null,"abstract":"In ASIC development, effective simulation leads into functionally more reliable chips as well as faster development time. This paper describes the design and the simulation techniques used in 3 ATM ASIC developments in ETRI. The three ASICs described are: ASAH-NIC-a 155 Mbps ATM SAR chip with internal PCI interface and SDH framer; ASAPI-L4-a 622 Mbps bidirectional ATM layer processing chip with UPC, OAM, QOS buffering capabilities; and ASAH-P4-a 622 Mbps ATM physical layer chip.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116003885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824070
Young-Ho Lee, Ki-Won Kwon, Jin-Tea Kim, Chul-Dong Lee
For efficient system-on-chip (SOC) design, we need an IP DB (intellectual property database) where everyone can register IP and access IP they want. To quickly collect and register IP from companies and universities, we have to give some benefits to the IP providers while minimizing the IP standard they must observe. To provide IP suitable for IP users, we have to have an IP DB which contains rated IP and has sufficient and convenient functions such as IP search, compare and download. Finally, to satisfy the various requirements of both IP providers and IP users, we have to have many business models and license models working in reality. We present KETI's works to solve these problems, focusing on the development and management of an IP DB.
{"title":"IP development and management of IP DB enabling efficient system-on-chip design","authors":"Young-Ho Lee, Ki-Won Kwon, Jin-Tea Kim, Chul-Dong Lee","doi":"10.1109/APASIC.1999.824070","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824070","url":null,"abstract":"For efficient system-on-chip (SOC) design, we need an IP DB (intellectual property database) where everyone can register IP and access IP they want. To quickly collect and register IP from companies and universities, we have to give some benefits to the IP providers while minimizing the IP standard they must observe. To provide IP suitable for IP users, we have to have an IP DB which contains rated IP and has sufficient and convenient functions such as IP search, compare and download. Finally, to satisfy the various requirements of both IP providers and IP users, we have to have many business models and license models working in reality. We present KETI's works to solve these problems, focusing on the development and management of an IP DB.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116379414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824073
J. Park, K. Yoon
This paper proposes a new SDM (sigma delta modulator) architecture to improve conversion rates and SNR (signal-to noise ratio). The characteristic of the proposed SDM employs an adaptive clocking architecture which includes the first integrator with a 1 MHz clock and the second/third integrator with a 4 MHz clock. The SDM circuit with a 0.65 um CMOS process is simulated by both MATLAB and HSPICE. The simulation results illustrate that SNRs of the proposed SDM are increased by 2 dB @internal 1 bit ADC/DAC and 7 dB @3 bit and 5 bit compared with the conventional SDM.
本文提出了一种新的SDM (σ δ调制器)结构，以提高转换率和信噪比。所提出的SDM的特性采用自适应时钟架构，其中包括具有1 MHz时钟的第一个积分器和具有4 MHz时钟的第二/第三个积分器。利用MATLAB和HSPICE对采用0.65 um CMOS工艺的SDM电路进行了仿真。仿真结果表明，与传统SDM相比，该SDM在内置1位ADC/DAC时信噪比提高了2 dB，在内置3位和5位时信噪比提高了7 dB。
{"title":"Design of a 3/sup rd/ order CMOS sigma-delta modulator with faster conversion rates using zero-pole canceling technique","authors":"J. Park, K. Yoon","doi":"10.1109/APASIC.1999.824073","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824073","url":null,"abstract":"This paper proposes a new SDM (sigma delta modulator) architecture to improve conversion rates and SNR (signal-to noise ratio). The characteristic of the proposed SDM employs an adaptive clocking architecture which includes the first integrator with a 1 MHz clock and the second/third integrator with a 4 MHz clock. The SDM circuit with a 0.65 um CMOS process is simulated by both MATLAB and HSPICE. The simulation results illustrate that SNRs of the proposed SDM are increased by 2 dB @internal 1 bit ADC/DAC and 7 dB @3 bit and 5 bit compared with the conventional SDM.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128696828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824027
Hee-Jin Yoo, Do-Soon Park
We propose a scheduling algorithm for the pipelined data path with resource constraint. The algorithm first checks the possibility of scheduling in the case of being assigned to the earliest step or to the latest step among the assignable control steps of all operations. If it is impossible to assign an operation to those steps due to resource constraint violation, the algorithm does away with those steps, that is, reduces the mobility of the operation. The scheduling algorithm is iterated until final schedule is obtained. If the final schedule is not obtained, even though there is no operation to reduce a mobility, we select a proper operation to reduce the mobility using the current scheduling state that is represented by parameters. A 16 point FIR filter and 5th order elliptic wavefilter are used to illustrate the scheduling algorithm.
{"title":"A scheduling algorithm for pipelined data path synthesis with gradual mobility reduction","authors":"Hee-Jin Yoo, Do-Soon Park","doi":"10.1109/APASIC.1999.824027","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824027","url":null,"abstract":"We propose a scheduling algorithm for the pipelined data path with resource constraint. The algorithm first checks the possibility of scheduling in the case of being assigned to the earliest step or to the latest step among the assignable control steps of all operations. If it is impossible to assign an operation to those steps due to resource constraint violation, the algorithm does away with those steps, that is, reduces the mobility of the operation. The scheduling algorithm is iterated until final schedule is obtained. If the final schedule is not obtained, even though there is no operation to reduce a mobility, we select a proper operation to reduce the mobility using the current scheduling state that is represented by parameters. A 16 point FIR filter and 5th order elliptic wavefilter are used to illustrate the scheduling algorithm.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129281375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824061
Kyeounsoo Kim, P. Beerel
This paper proposes a low-overhead MSB-controlled inversion coding technique to reduce the transition activity in a matrix transposer a commonly used component in 2-dimensional discrete cosine transform (DCT) and inverse DCT (IDCT) applications. A family of designs is identified in which this technique is applied to different bit slices of the matrix data and the optimal design within the family is determined using transition activity analysis driven by real image sequences. Our results suggest that the optimal design using MSB-controlled inversion coding yields power savings of 33% for DCT data and 46% for IDCT data. These results are remarkable since existing bus-invert coding techniques have high overheads and are only effective for system-level high-capacitive buses.
{"title":"A low-power matrix transposer using MSB-controlled inversion coding","authors":"Kyeounsoo Kim, P. Beerel","doi":"10.1109/APASIC.1999.824061","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824061","url":null,"abstract":"This paper proposes a low-overhead MSB-controlled inversion coding technique to reduce the transition activity in a matrix transposer a commonly used component in 2-dimensional discrete cosine transform (DCT) and inverse DCT (IDCT) applications. A family of designs is identified in which this technique is applied to different bit slices of the matrix data and the optimal design within the family is determined using transition activity analysis driven by real image sequences. Our results suggest that the optimal design using MSB-controlled inversion coding yields power savings of 33% for DCT data and 46% for IDCT data. These results are remarkable since existing bus-invert coding techniques have high overheads and are only effective for system-level high-capacitive buses.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"192 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116494500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824051
Byungjoon Song, Hwi-Cheol Kim, Youngdon Choi, Wonchan Kim
In this paper, a CMOS relaxation oscillator is presented. The proposed oscillator has only one tail current source unlike the emitter coupled multivibrator. All the tail current flows through the timing capacitor and thus the charging slope of the timing capacitor is doubled. This enhances the operating speed without increasing the power consumption. The oscillator is fabricated in a standard 0.8 /spl mu/m CMOS process. The maximum operating frequency is 923 MHz at a 3.3 V single supply, while the oscillator draws 6 mA.
{"title":"A 50% power reduction scheme for CMOS relaxation oscillator","authors":"Byungjoon Song, Hwi-Cheol Kim, Youngdon Choi, Wonchan Kim","doi":"10.1109/APASIC.1999.824051","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824051","url":null,"abstract":"In this paper, a CMOS relaxation oscillator is presented. The proposed oscillator has only one tail current source unlike the emitter coupled multivibrator. All the tail current flows through the timing capacitor and thus the charging slope of the timing capacitor is doubled. This enhances the operating speed without increasing the power consumption. The oscillator is fabricated in a standard 0.8 /spl mu/m CMOS process. The maximum operating frequency is 923 MHz at a 3.3 V single supply, while the oscillator draws 6 mA.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114026484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-08-23DOI: 10.1109/APASIC.1999.824040
Moon Gyung Rim, B. Moon, S. An, D. Ryu, Y. S. Lee
This paper presents an approach to establish and simulate a DSP core by using a cycle-based simulator written in C language. The simulator is written with information of a target DSP core. Instructions are analyzed in order to determine which blocks are used. Then, appropriate control signals are applied to the blocks. The implemented simulator can give the cycle-based information such as changes of control signals and register flags that are not given by instruction-based simulators. After modeling and validating the simulator it is used to verify the HDL model of target DSP core and to enhance its performance as well as to develop applications for the core.
{"title":"Implementation of a cycle-based simulator for the design of a processor core","authors":"Moon Gyung Rim, B. Moon, S. An, D. Ryu, Y. S. Lee","doi":"10.1109/APASIC.1999.824040","DOIUrl":"https://doi.org/10.1109/APASIC.1999.824040","url":null,"abstract":"This paper presents an approach to establish and simulate a DSP core by using a cycle-based simulator written in C language. The simulator is written with information of a target DSP core. Instructions are analyzed in order to determine which blocks are used. Then, appropriate control signals are applied to the blocks. The implemented simulator can give the cycle-based information such as changes of control signals and register flags that are not given by instruction-based simulators. After modeling and validating the simulator it is used to verify the HDL model of target DSP core and to enhance its performance as well as to develop applications for the core.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"197 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114874391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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