{"title":"A generic AHB bus for implementing high-speed locally synchronous islands","authors":"M. Dubois, Y. Savaria, G. Bois","doi":"10.1109/SECON.2005.1423208","DOIUrl":null,"url":null,"abstract":"Platform-based design requires flexibility and compatibility between components in order to design derivative applications without changing hardware or software. Several solutions are available, but they lack either the necessary throughput or flexibility. The paper proposes a generic multi-frequency interconnection infrastructure module that facilitates development of flexible on-chip high-performance buses. It is based on the AMBA high-speed bus (AHB). The proposed architecture has been implemented with the HDL Designer environment and laid out as a 0.18 /spl mu/m CMOS module using Synopsys tools to validate the proposed concepts.","PeriodicalId":129377,"journal":{"name":"Proceedings. IEEE SoutheastCon, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. IEEE SoutheastCon, 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SECON.2005.1423208","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
Platform-based design requires flexibility and compatibility between components in order to design derivative applications without changing hardware or software. Several solutions are available, but they lack either the necessary throughput or flexibility. The paper proposes a generic multi-frequency interconnection infrastructure module that facilitates development of flexible on-chip high-performance buses. It is based on the AMBA high-speed bus (AHB). The proposed architecture has been implemented with the HDL Designer environment and laid out as a 0.18 /spl mu/m CMOS module using Synopsys tools to validate the proposed concepts.