Conditions of CM voltage cancellation in multilevel voltage inverters with conventional and improved carrier-based SVPWM

A. Kempski, R. Smoleński, P. Lezynski
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引用次数: 4

Abstract

In the paper we have investigated the EMC aspects of the proposed modulation algorithm in the comparison with the conventional carrier-based SVPWM. Our results showed that the choice of this modulation causes that the conditions for the compensation, by means of zero common mode (CM) voltage filter, become more favorable then in a case of the conventional SVPWM. In spite of the fact that frequencies of gate pulses are the same in both modulations, the CM voltage frequency is doubled. The time durations of the CM voltage shelves decreases twice and consequently the time integral value of the CM voltage and the magnetizing current decrease as well. This results in reduction of the size, weight and cost of inductive components of filters in multilevel drives.
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基于传统和改进载波的SVPWM多电平逆变器中CM电压对消条件
在本文中,我们研究了所提出的调制算法的电磁兼容方面,并与传统的基于载波的SVPWM进行了比较。结果表明,这种调制方式的选择使得零共模(CM)电压滤波器的补偿条件比传统的SVPWM更有利。尽管栅极脉冲的频率在两种调制中是相同的,但CM电压频率增加了一倍。CM电压架的持续时间缩短了两倍,从而CM电压和磁化电流的时间积分值也减小了。这就减少了多电平驱动器中滤波器电感元件的尺寸、重量和成本。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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Instantaneous single-phase system power demonstration using virtual two phase theory Power quality conditioners with minimum number of current sensor requirement Power electronics active filter with controlled dynamics Conditions of CM voltage cancellation in multilevel voltage inverters with conventional and improved carrier-based SVPWM Natural doubling of the apparent switching frequency using three-level ANPC converter
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