Ishmael Sameen, Yoong Choon Chang, N. Song, B. Goi, Chee Siong Lee
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Abstract
This paper proposes a programmable 2-D DWT system architecture designed for the JPEG-2000 standard. The proposed system architecture, derived from an iterative design space exploration process using Altera's C2H compiler, provides a significant performance acceleration of 2-D DWT when compared to an optimized 2-D DWT software implementation and is capable of real-time video processing performance up to 720p (1280 × 720) image resolutions when synthesized and tested on an Altera DE3 Stratix III FPGA board.
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