Register Caching as a Way of Mitigating Intercluster Communication Penalties in Clustered Microarchitectures

Abstract

Two important factors in any clustered microarchitecture are the intercluster communication penalties (involved when importing operands from another cluster) and workload balance (involves the balanced utilization of each cluster's computing resources). The goal in any design undertaking is to minimize the former and maximize the latter, failure in any of which would degrade the microarchitecture's performance. A novel technique that could mitigate intercluster communication penalties, called register caching, is explored in this paper. Register caching involves buffering or caching a very small number of register or operand values imported from another cluster (and thus having incurred intercluster communication penalty) with the hopes that they'd be referenced again without being modified. Should the said referencing happen, the cluster would no longer have to import the values again, and intercluster communication penalty savings are incurred. Effectiveness of replacement algorithms, necessary since the register cache would be full most of the time, would be explored in this paper, along with the technique's performance as a function of register cache size and intercluster communication latency values.